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MASH 2-2 CTΔΣM with Fully Integrated Quantization Noise Leakage Calibration

  • Qiyuan Liu
  • Alexander Edward
  • Carlos Briseno-Vidrios
  • Jose Silva-Martinez
Chapter

Abstract

This chapter presents a MASH 2-2 CTΔΣM with on-chip RC time-constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise cancelation filter (NCF). The core modulator architecture is a cascade of two single-loop second-order CTΔΣM stages, each of which consists of an integrator-based active-RC loop filter, current-steering feedback digital-to-analog converters, and a four-bit Flash quantizer. On-chip RC time-constant calibration circuits and high-gain multi-stage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to (1) synthesize a fourth-order noise transfer function with DC zeros, (2) simplify the design of NCF, and (3) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40 nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise and distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43 mW of power (P) from 1.1, 1.15, and 2.5-V power supplies. It does not require external software calibration and possesses minimal out-of-band signal transfer function (STF) peaking.

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Qiyuan Liu
    • 1
  • Alexander Edward
    • 2
  • Carlos Briseno-Vidrios
    • 3
  • Jose Silva-Martinez
    • 4
  1. 1.Qualcomm IncorporatedTempeUSA
  2. 2.Intel CorporationHillsboroUSA
  3. 3.Silicon Laboratories IncorporatedAustinUSA
  4. 4.Department of Electrical and Computer EngineeringTexas A&M UniversityCollege StationUSA

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