Skip to main content

Design of Continuous-Time Delta-Sigma Modulators

  • Chapter
  • First Online:
Design Techniques for Mash Continuous-Time Delta-Sigma Modulators

Abstract

This chapter presents the analysis and design of continuous-time ΔΣ modulators (CTΔΣMs) with a focus on single-loop topology. The methodology of mapping the noise transfer function (NTF) from discrete-time to continuous-time is explained with a design example of a fifth-order CTΔΣM. The anti-aliasing characteristics of feedback and feedforward loop filter topologies are compared. The effects of non-idealities such as the excess loop delay (ELD) and the feedback DAC’s clock jitter on the performance of CTΔΣMs are discussed. A 75-MHz single-loop CTΔΣM prototype is presented as a design example. It was fabricated in a low-power 40-nm CMOS technology, employing a broadband low-power highly efficient common-gate summing stage. This knowledge on single-loop CTΔΣMs is fundamental for the analysis and design of MASH CTΔΣMs.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    This Sect. 4.1.6 includes portions reprinted with permission from A. Edward and J. Silva-Martinez.: General analysis of feedback DAC’s clock jitter in continuous-time delta-sigma modulators. IEEE Trans. Circuits and Systems – II (TCAS-II) 61(7), 506–510 (2014), Ⓒ2014 IEEE

  2. 2.

    This Sect. 4.2 includes portions reprinted with permission from C. Briseno-Vidrios, A. Edward, A. Shafik, S. Palermo, and J. Silva-Martinez.: A 75-MHz continuous-time delta-sigma modulator employing a broadband low-power highly efficient common-gate summing stage. IEEE J. Solid-State Circuits (JSSC) 52(3), 657–667 (2017), Ⓒ2017 IEEE

References

  1. R. Schreier, Delta sigma toolbox [Online] (2016). Available: http://www.mathworks.com/matlabcentral/fileexchange/19-delta-sigma-toolbox

  2. J.A. Cherry, W.M. Snelgrove, Clock jitter and quantizer metastability in continuous-time delta-sigma modulators. IEEE Trans. Circuits Syst. II 46(6), 661–676 (1999)

    Article  Google Scholar 

  3. H. Tao, L. Toth, J.M. Khoury, Analysis of timing jitter in bandpass sigma-delta modulators. IEEE Trans. Circuits Syst. II 46(8), 991–1001 (1999)

    Article  Google Scholar 

  4. R. Saad, D.L. Aristizabal-Ramirez, S. Hoyos, Sensitivity analysis of continuous-time ΔΣ ADCs to out-of-band blockers in future SAW-less multi-standard wireless receivers. IEEE Trans. Circuits Syst. I 59(9), 1894–1905 (2012)

    Article  MathSciNet  Google Scholar 

  5. L. Hernandez, A. Wiesbauer, S. Paton, A. Di Giandomenico, Modelling and optimization of low pass continuous-time sigma-delta modulators for clock jitter noise reduction, in IEEE Int. Symp. Circuits and Systems, Vancouver (2004), pp. 1072–1075

    Google Scholar 

  6. K. Reddy, S. Pavan, Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter. IEEE Trans. Circuits Syst. I 54(10), 2184–2194 (2007)

    Article  Google Scholar 

  7. Y.-S. Chang, C.-L. Lin, W.-S. Wang, C.-C. Lee, C.-Y. Shih, An analytical approach for quantifying clock jitter effects in continuous-time sigma-delta modulators. IEEE Trans. Circuits Syst. I 53(9), 1861–1168 (2006)

    Article  Google Scholar 

  8. R. van Veldhoven, P. Nuijten, P. van Zeijl, The effect of clock jitter on the DR of ΣΔ modulators, in IEEE Int. Symp. Circuits and Systems, Island of Kos (2006), pp. 2009–2012

    Google Scholar 

  9. A.M. Thurston, T.H. Pearce, M.J. Hawksford, Bandpass implementation of the sigma-delta A-D conversion technique, in Int. Conf. Analogue to Digital and Digital to Analogue Conversion, Swansea (1991), pp. 81–86

    Google Scholar 

  10. F.M. Gardner, A transformation for digital simulation of analog filters. IEEE Trans. Commun. 34(7), 676–680 (1986)

    Article  Google Scholar 

  11. M. Ortmanns, F. Gerfers, Y. Manoli, A continuous-time ΣΔ modulator with reduced sensitivity to clock jitter through SCR feedback. IEEE Trans. Circuits Syst. I 52(5), 875–884 (2005)

    Article  MathSciNet  MATH  Google Scholar 

  12. O. Oliaei, Sigma-delta modulator with spectrally shaped feedback. IEEE Trans. Circuits Syst. II 50(9), 518–530 (2003)

    Article  MathSciNet  Google Scholar 

  13. M. Schetzen, The Volterra and Wiener Theories of Nonlinear Systems (Krieger, Malabar, FL, 2006)

    MATH  Google Scholar 

  14. S. Paton, A. Di Giandomenico, L. Hernandez, A. Wiesbauer, T. Potscher, M. Clara, A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution. IEEE J. Solid State Circuits 39(7), 1056–1063 (2004)

    Article  Google Scholar 

  15. C.-Y. Lu, M. Onabajo, V. Gadde, Y.-C, Lo, H.-P. Chen, V. Periasamy, J. Silva-Martinez, A 25 MHz bandwidth 5th-order continuous-time low-pass sigma-delta modulator with 67.7 dB SNDR using time-domain quantization and feedback. IEEE J. Solid State Circuits 45(9), 1795–1808 (2010)

    Google Scholar 

  16. M. Bolatkale, L.J. Breems, R. Rutten, K.A. Makinwa, A 4GHz continuous-time ΣΔ ADC with 70 dB DR and −74 dBFS THD in 125 MHz BW. IEEE J. Solid State Circuits 45(9), 1795–1808 (2010)

    Article  Google Scholar 

  17. H. Shibata, R. Schreier, W. Yang, A. Shaikh, D. Paterson, T.C. Caldwell, D. Alldred, P.W. Lai, A DC-to-1 GHz tunable RF ΔΣ ADC achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz using 550 mW. IEEE J. Solid State Circuits 47(12), 2888–2897 (2012)

    Article  Google Scholar 

  18. V. Srinivasan, V. Wang, P. Satarzadeh, B. Haroun, M. Corsi, A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS, in IEEE Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco (2012), pp. 158–160

    Google Scholar 

  19. M. Andersson, M. Anderson, L. Sundstrom, S. Mattisson, P. Andreani, A filtering ΔΣ ADC for LTE and beyond. IEEE J. Solid State Circuits 49(7), 1535–1547 (2014)

    Article  Google Scholar 

  20. Y. Dong, W. Yang, R. Schreier, A. Sheikholeslami, S. Korrapati, A continuous-time 0–3 MASH ADC achieving 88 dB DR with 53 MHz BW in 28 nm CMOS. IEEE J. Solid State Circuits 49(12), 2868–2877 (2014)

    Article  Google Scholar 

  21. J.G. Kauffman, P. Witte, M. Lehmann, J. Becker, Y. Manoli, M. Ortmanns, A 72 dB DR, CT ΔΣ modulator using digitally estimated, auxiliary DAC linearization achieving 88 fJ/conv-step in a 25 MHz Bw. IEEE J. Solid State Circuits 49(2), 392–404 (2014)

    Article  Google Scholar 

  22. D.Y. Yong, S. Ho, H.S. Lee, A continuous-time sturdy-MASH ΔΣ modulator in 28 nm CMOS. IEEE J. Solid State Circuits 50(12), 2880–2890 (2015)

    Article  Google Scholar 

  23. S. Ho, C.L. Lo, J. Ru, J. Zhao, A 23 mW, 73 dB dynamic range, 80 MHz BW continuous-time delta-sigma modulator in 20 nm CMOS. IEEE J. Solid State Circuits 50(4), 908–919 (2015)

    Article  Google Scholar 

  24. C. Briseno-Vidrios, A. Edward, A. Shafik, S. Palermo, J. Silva-Martinez, A 75 MHz BW 68dB DR CT-ΔΣ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique, in IEEE Int. Symp. VLSI Circuits (VLSI) Dig. Tech. Papers, Kyoto (2015), pp. C254–C255

    Google Scholar 

  25. R. Zanbaghi, P.K. Hanumolu, T.S. Fiez, An 80-dB DR, 7.2-MHz bandwidth single opamp biquad based CT ΔΣ modulator dissipating 13.7-mW. IEEE J. Solid State Circuits 48(2), 487–501 (2013)

    Google Scholar 

  26. C.-H. Weng, T.-A. Wei, E. Alpman, C.-T. Fu, T.-H. Lin, A continuous-time delta-sigma modulator using ELD-compensation embedded SAB and DWA-inherent time-domain quantizer. IEEE J. Solid State Circuits 51(5), 1235–1245 (2016)

    Article  Google Scholar 

  27. S. Zeller, C. Muenker, R. Weigel, U. Ussmueller, A 0.0039 mm2 inverter-based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT-ΣΔ ADC in 65 nm CMOS using power- and area-efficient design techniques. IEEE J. Solid State Circuits 49(7), 1548–1560 (2014)

    Google Scholar 

  28. S. Yan, E. Sanchez-Sinencio, A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth. IEEE J. Solid State Circuits 39(1), 75–86 (2004)

    Google Scholar 

  29. Y.-S. Shu, J.-Y. Tsai, P. Chen, T.-Y. Lo, P.-C. Chiu, A 28fJ/conv-step CT ΣΔ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer, in IEEE Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco (2013), pp. 268–269

    Google Scholar 

  30. S. Ho, C.-L. Lo, J. Ru, J. Zhao, A 23 mW, 73 dB dynamic range, 80 MHz BW continuous-time delta-sigma modulator in 20 nm CMOS, in IEEE Int. Symp. VLSI Circuits (VLSI) Dig. Tech. Papers, Honolulu (2014), pp. 1–2

    Google Scholar 

  31. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, E. Romani, A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth. IEEE J. Solid State Circuits 41(12), 2641–2649 (2006)

    Article  Google Scholar 

  32. C. Briseno-Vidrios, A. Edward, N. Rashidi, J. Silva-Martinez, A 4 bit continuous-time sigma-delta modulator with fully digital quantization noise reduction algorithm employing a 7 bit quantizer. IEEE J. Solid State Circ. 51(6), 1398–1409 (2016)

    Article  Google Scholar 

  33. C.-J. Park, M. Onabajo, H.M. Geddada, A.I. Karsilayan, J. Silva-Martinez, Efficient broadband current-mode adder-quantizer design for continuous-time sigma-delta modulators. IEEE Trans. Very Large Scale Integr. Syst. 23(9), 1902–1930 (2015)

    Article  Google Scholar 

  34. B.K. Thandri, J. Silva-Martinez, A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors. IEEE J. Solid State Circuits 38(2), 237–243 (2003)

    Article  Google Scholar 

  35. B.C. Kuo, Automatic Control Systems (Prentice-Hall, Eaglewood Cliffs, 1981)

    Google Scholar 

  36. K. Falakshahi, C.-K.K. Yang, B.A. Wooley, A 14-bit 10-Msamples/s D/A converter using multibit ΣΔ modulation. IEEE J. Solid State Circuits 34(5), 607–615 (1999)

    Article  Google Scholar 

  37. M. Matsui, H. Hara, Y. Uetani, L.-S. Kim, T. Nagamatsu, Y. Watanable, A. Chiba, K. Matsuda, T. Sakurai, A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme. IEEE J. Solid State Circuits 29(12), 1482–1490 (1994)

    Article  Google Scholar 

  38. B. Nikolic, V.G. Oklobdzija, V. Stojanovic, W. Jia, J.K.-S. Chiu, M.M.-T. Leung, Improved sense-amplifier-based flip-flop: design and measurements. IEEE J. Solid State Circuits 35(6), 876–884 (2000)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer International Publishing AG, part of Springer Nature

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Liu, Q., Edward, A., Briseno-Vidrios, C., Silva-Martinez, J. (2018). Design of Continuous-Time Delta-Sigma Modulators. In: Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer, Cham. https://doi.org/10.1007/978-3-319-77225-7_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-77225-7_4

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-77224-0

  • Online ISBN: 978-3-319-77225-7

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics