Abstract
This chapter presents the analysis and design of continuous-time ΔΣ modulators (CTΔΣMs) with a focus on single-loop topology. The methodology of mapping the noise transfer function (NTF) from discrete-time to continuous-time is explained with a design example of a fifth-order CTΔΣM. The anti-aliasing characteristics of feedback and feedforward loop filter topologies are compared. The effects of non-idealities such as the excess loop delay (ELD) and the feedback DAC’s clock jitter on the performance of CTΔΣMs are discussed. A 75-MHz single-loop CTΔΣM prototype is presented as a design example. It was fabricated in a low-power 40-nm CMOS technology, employing a broadband low-power highly efficient common-gate summing stage. This knowledge on single-loop CTΔΣMs is fundamental for the analysis and design of MASH CTΔΣMs.
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Notes
- 1.
This Sect. 4.1.6 includes portions reprinted with permission from A. Edward and J. Silva-Martinez.: General analysis of feedback DAC’s clock jitter in continuous-time delta-sigma modulators. IEEE Trans. Circuits and Systems – II (TCAS-II) 61(7), 506–510 (2014), Ⓒ2014 IEEE
- 2.
This Sect. 4.2 includes portions reprinted with permission from C. Briseno-Vidrios, A. Edward, A. Shafik, S. Palermo, and J. Silva-Martinez.: A 75-MHz continuous-time delta-sigma modulator employing a broadband low-power highly efficient common-gate summing stage. IEEE J. Solid-State Circuits (JSSC) 52(3), 657–667 (2017), Ⓒ2017 IEEE
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Liu, Q., Edward, A., Briseno-Vidrios, C., Silva-Martinez, J. (2018). Design of Continuous-Time Delta-Sigma Modulators. In: Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer, Cham. https://doi.org/10.1007/978-3-319-77225-7_4
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