Abstract
Advanced nanometre CMOS processes, with channel lengths below 100 nm, have emerged from the numerous manufacturing processes that have evolved since the introduction of the MOS transistor in integrated circuits during the 1970s. Often the process-related discussions are either focussed towards that part of the process in which the transistors are fabricated or towards the part in which the contacts and interconnections are fabricated. These parts are called front-end process and back-end process, respectively.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
Note: Not every reader has access to the published articles of microelectronic conferences and magazines. A lot of effort has therefore been given to refer to those publications that are directly accessible through web pages on the Internet. However, these data may be volatile because some owners update and change the contents on their web pages, so that some of the references below may only be accessible during a short time after the print of this book. Finally a lot more information on the various subjects can be found by searching the Web with the right entry, which can be easily extracted from the corresponding subject. Good Luck!
References
Note: Not every reader has access to the published articles of microelectronic conferences and magazines. A lot of effort has therefore been given to refer to those publications that are directly accessible through web pages on the Internet. However, these data may be volatile because some owners update and change the contents on their web pages, so that some of the references below may only be accessible during a short time after the print of this book. Finally a lot more information on the various subjects can be found by searching the Web with the right entry, which can be easily extracted from the corresponding subject. Good Luck!
Intel White Paper, “Introducing the 45nmNext-Generation Intel® Core™ Microarchitecture”, <www.intel.com/technology/architecture-silicon/intel64/45nm-core2_whitepaper.pdf>
Laura Peters, “Gaining Control over STI Processes”, <www.jysong.idv.tw/cu/articles/cu0011.htm>
James Kawski, et al., “Ion implant: a new enabler for 32nm and 22nm devices”, <www.electroiq.com/index/display/semiconductors-article-display/355567/articles/solid-state-technology/volume-52/issue-3/features/cover-article/ion-implant-a-new-enabler-for-32nm-and-22nm-devices.html>
Wang Zhengfeng, “Chemical Mechanical Planarization”, <http://maltiel-consulting.com/CMP-Chemical-mechanical_planarization_maltiel_semiconductor.pdf>
Harry J.M. Veendrick, “Nanometer CMOS ICs, from Basics to ASICs”, ISBN 978-3-319-47597-4, Springer 2017
Scott E. Thompson, “Uniaxial-Process-Induced Strained-Si: Extending the CMOS Roadmap”, IEEE Transactions on Electron Devices, Vol.53, No.5, May 2006, <www.thompson.ece.ufl.edu/Fall2008/TED-%20extending%20roadmap-01624680.pdf>
Min-hwa Chi, “Challenges in Manufacturing FinFET at 20 nm node and beyond”, http://www.rit.edu/kgcoe/eme/sites/default/_les/Minhwa%20Chi%20-%20abstract%20Challenges%20in%20Manufacturing%20FinFET.pdf
Dylan McGrath, “Few Surprises as Intel, GF Detail Process Technologies”, EE|Times, 12/7/2017
ITRS Roadmap Report, 2015 edition, https://www.semiconductors.org/main/2015_international_technology_roadmap_for_semiconductors_itrs/
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer International Publishing AG, part of Springer Nature
About this chapter
Cite this chapter
Veendrick, H. (2019). Fabrication. In: Bits on Chips. Springer, Cham. https://doi.org/10.1007/978-3-319-76096-4_10
Download citation
DOI: https://doi.org/10.1007/978-3-319-76096-4_10
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-76095-7
Online ISBN: 978-3-319-76096-4
eBook Packages: EngineeringEngineering (R0)