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Timing Performance of Nanometer Digital Circuits Under Process Variations pp 143–163Cite as

Designing with FinFETs and Process Variation Impact

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Part of the book series: Frontiers in Electronic Testing ((FRET,volume 39))

Abstract

Scaled planar transistor devices present significant increases of the leakage current exacerbated by process variations, which limits the performance of some electronic applications. FinFET technology has been adopted starting 22 nm technology node for high-performance and power-efficient applications. This chapter introduces FinFET devices. The fabrication steps for making fins and middle-of-line (MOL) local interconnects are described. Design issues unique to FinFET technology are discussed. A step-by-step procedure to create the layout of an inverter cell is presented. The main sources of process variations in FinFET technology are analyzed, and their impact on the delay performance of logic cells is discussed. The computing of the delay variance (standard deviation) of an inverter gate based on FinFET technology is presented. A hand-by-hand example of computing the delay of a single logic cell is presented.

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Authors and Affiliations

  1. INAOE, Tonantzintla, Puebla, Mexico

    Victor Champac

  2. Universidad Veracruzana, Xalapa, Veracruz, Mexico

    Jose Garcia Gervacio

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  1. Victor Champac
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  2. Jose Garcia Gervacio
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Champac, V., Garcia Gervacio, J. (2018). Designing with FinFETs and Process Variation Impact. In: Timing Performance of Nanometer Digital Circuits Under Process Variations. Frontiers in Electronic Testing, vol 39. Springer, Cham. https://doi.org/10.1007/978-3-319-75465-9_7

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  • DOI: https://doi.org/10.1007/978-3-319-75465-9_7

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  • Online ISBN: 978-3-319-75465-9

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