Abstract
The previous chapter described the statistical delay under process variations of a digital gate. This chapter studies the statistical performance of a logic path composed of several gates under process variations. It is shown how to compute the delay variance (standard deviation) of a logic path. This is illustrated in detail for a two-inverter chain, and then this analysis is extended to a general logic path. Pure random and correlated variations are considered. The behavior of a logic path under process variations is analyzed. Several key design issues affecting the path delay are illustrated such as the impact of spatial correlation, the influence of relative delay sensitivities between gates, sizing a logic path, and logic depth. Based on the previous key design issues, designers can take actions to improve their designs and fulfill timing specifications efficiently. In the last issue addressed in this chapter, the main advantages of statistical-based design over corner-based design are analyzed. Overheads due to pessimistic corner design are increasing and becoming non-tolerable in nanometer digital circuits.
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Champac, V., Garcia Gervacio, J. (2018). Path Delay Under Process Variations. In: Timing Performance of Nanometer Digital Circuits Under Process Variations. Frontiers in Electronic Testing, vol 39. Springer, Cham. https://doi.org/10.1007/978-3-319-75465-9_5
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