Abstract
The previous chapter described the nature of the variations of the technological parameters due to the fabrication process. The behavior of correlated and pure random variations was illustrated. This chapter studies the impact of these variations on the statistical performance of logic cells. First, the statistical delay of a logic gate is obtained using simple mathematical formulation. A detailed statistical analysis is devoted to the inverter gate, which due to its simple structure allows an in-depth analysis of its statistical performance. It is shown how to compute the statistical inverter delay. Next, the statistical treatment is extended to a 2-Nand gate. This multi-input gate allows illustrating important related aspects with the serial/parallel connection of transistors that influence the statistical performance. The statistical analysis is generalized to other types of logic gates such as Nor, EX-OR, and AOI/AIO gates. Hand-by-hand examples to compute the delay variance (standard deviation) of logic gates are presented. The behavior of the delay variance of logic gates with relevant circuit parameters is analyzed. Several key design issues affecting the gate delay are illustrated such as sizing a logic gate, load capacitance, input slew time, power supply voltage, and gate delay dependence on input transition.
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Champac, V., Garcia Gervacio, J. (2018). Gate Delay Under Process Variations. In: Timing Performance of Nanometer Digital Circuits Under Process Variations. Frontiers in Electronic Testing, vol 39. Springer, Cham. https://doi.org/10.1007/978-3-319-75465-9_4
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