Skip to main content
SpringerLink
Log in

Introduction

  • Chapter
  • First Online:
Timing Performance of Nanometer Digital Circuits Under Process Variations

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 39))

  • 953 Accesses

Abstract

This chapter provides the general framework for the book. An overview of the semiconductor technology evolution through years is presented, and the main driving forces for technology scaling are presented. A design flow for modern digital integrated circuits to obtain a final designed circuit working on required performance within product specifications is described, and the role of process variations to achieve the previous goals is outlined. The corner design methodology, widely used in industry to deal with process variations, and how statistical analysis overcomes its limitations are discussed.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 129.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 129.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. R. Reid, The CHIP: How Two Americans Invented the Microchip and Launched a Revolution, 2nd edn. (Random House Trade Paperbacks, New York, 2001)

    Google Scholar 

  2. F. Maloberti, A.C. Davos, A Short Story of Circuits and Systems (IEEE/Rivers Publishers, New York/Aalborg, 2016)

    Google Scholar 

  3. J. Bardeen, W.H. Brattain, Physical principles involved in transistor action. Bell Syst. Tech. J. 28(2), 239–277 (1949). https://doi.org/10.1002/j.1538-7305.1949.tb03634.x

  4. C. Piguet, History of low-power electronics, in Low-Power CMOS Circuits Technology, Logic Design and CAD Tools, ed. by C. Piguet. (Taylor and Francis Group, Boca Raton, 2006)

    Google Scholar 

  5. W. Shockley, A unipolar “field-effect” transistor. Proc. IRE 40(11), 1365–1376 (1952). https://doi.org/10.1109/JRPROC.1952.273964

  6. B. Razavi, Fundamentals of Microelectronics (Wiley India, Bangalore, 2009)

    Google Scholar 

  7. A.S. Sedra, K.C. Smith, Microelectronic Circuits, vol. 1 (Oxford University Press, New York, 1998)

    Google Scholar 

  8. R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, 3rd edn. (Wiley-IEEE Press, New York, 2010)

    Google Scholar 

  9. C. Kleint, Julius Edgar Lilienfeld: life and profession. Prog. Surf. Sci. 57(4), 253–327 (1998). ISSN 0079-6816

    Google Scholar 

  10. D. Kahng, Electric field controlled semiconductor device, U. S. Patent No. 3,102,230 (Filed 31 May 31, 1960, issued August 27, 1963)

    Google Scholar 

  11. S. Chih-Tan, Evolution of the MOS transistor-from conception to VLSI. Proc. IEEE 76(10), 1280–1326 (1988). https://doi.org/10.1109/5.16328

  12. N.H.E. Weste, D.M. Harris, CMOS VLSI Design A Circuit and Systems Perspective, 4th edn. (Addison Wesley, Boston, 2011)

    Google Scholar 

  13. C. Hu, New CMOS devices and compact modeling, in 2007 International Workshop on Physics of Semiconductor Devices, Mumbai, 2007, pp. 5–7. https://doi.org/10.1109/IWPSD.2007.4472441

  14. T. Cui, Q. Xie, Y. Wang, S. Nazarian, M. Pedram, 7 nm FinFET standard cell layout characterization and power density prediction in near- and super-threshold voltage regimes, in International Green Computing Conference, Dallas, TX, 2014, pp. 1–7. https://doi.org/10.1109/IGCC.2014.7039170

  15. L. Chang, K.J. Yang, Y.-C. Yeo, Y.-K. Choi, T.-J. King, C. Hu, Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs, in International Electron Devices Meeting. Technical Digest, Washington, DC, 2001, pp. 5.2.1–5.2.4. https://doi.org/10.1109/IEDM.2001.979428

  16. B. Yu et al., FinFET scaling to 10 nm gate length, in Digest. International Electron Devices Meeting, San Francisco, CA, 2002, pp. 251–254. https://doi.org/10.1109/IEDM.2002.1175825

  17. S.K. Hadia, R.R. Patel, Y.P. Kosta, FinFET architecture analysis and fabrication mechanism. Int. J. Comput. Sci. Issues 8(5), 235–240 (2011)

    Google Scholar 

  18. P. Mishra, A. Muttreja, N.K. Jha, FinFET circuit design, in Nanoelectronic Circuit Design, ed. by N. Jha, D. Chen (Springer, New York, 2011)

    Google Scholar 

  19. J.S. Kilby, The integrated circuit’s early history. Proc. IEEE 88(1), 109–111 (2000). https://doi.org/10.1109/5.811607

  20. In Memoriam - Jack Kilby (1923–2005) Inventor of the integrated circuit. IEEE Signal Process. Mag. 22(5), 6–7 (2005). https://doi.org/10.1109/MSP.2005.1511813

  21. M.J. Riezenman, Wanlass’s CMOS circuit. IEEE Spectr. 28(5), 44 (1991). https://doi.org/10.1109/6.83438

  22. F.M. Wanlass, Low stand-by power complementary field effect circuitry, US Patent 3,356,858, Google Patents, 1967

    Google Scholar 

  23. H. Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, 1st edn. (Cambridge University Press, New York, 2008)

    Google Scholar 

  24. M. Dietrich, J. Haase, Process Variations and Probabilistic Integrated Circuit Design (Springer, New York, 2012)

    Google Scholar 

  25. M. Wirnshofer, Sources of Variation (Springer Netherlands, Dordrecht, 2013), pp. 5–14

    Google Scholar 

  26. C. Forzan, D. Pandini, Statistical static timing analysis: a survey. Integr. VLSI J. 42(3), 409–435 (2009). Special Section on DCIS2006

    Google Scholar 

  27. S.S. Chung, The variability issues in small scale trigate cmos devices: random dopant and trap induced fluctuations, in Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), July 2013, pp. 173–176

    Google Scholar 

  28. A. Asenov, Statistical device variability and its impact on design, in 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems, April 2008, pp. xv–xvi

    Google Scholar 

  29. J. Kao, A.P. Chandrakasan, Dual-threshold voltage techniques for low-power digital circuits. IEEE J. Solid State Circuits 35, 1009–1018 (2000)

    Google Scholar 

  30. N. Sirisantana, L. Wei, K. Roy, High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness, in International Conference on Computer Design, 2000, pp. 227–232

    Google Scholar 

  31. B.P. Wong, A. Mittal, Y. Cao, G. Starr, Nano-CMOS Circuit and Physical Design (Wiley-Interscience, New York, 2005)

    Google Scholar 

  32. V. Melikyan, E. Babayan, A. Melikyan, D. Babayan, P. Petrosyan, E. Mkrtchyan, Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor, in 2015 IEEE East-West Design & Test Symposium (EWDTS), Batumi, 2015, pp. 1–4. https://doi.org/10.1109/EWDTS.2015.7493159

  33. V. Melikyan, T. Hakhverdyan, S. Manukyan, A. Gevorgyan, D. Babayan, Low power OpenRISC processor with power gating, multi-VTH and multi-voltage techniques, in 2016 IEEE East-West Design & Test Symposium (EWDTS), Yerevan, 2016, pp. 1–4. https://doi.org/10.1109/EWDTS.2016.7807678

  34. S.A. Tawfik, V. Kursun, Low power and high speed multi threshold voltage interface circuits. IEEE Trans. Very Large Scale Integr. VLSI Syst. 17, 638–645 (2009)

    Google Scholar 

  35. B. Amelifard, F. Fallah, M. Pedram, Low-power fanout optimization using multi threshold voltages and multi channel lengths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4), 478–489 (2009). https://doi.org/10.1109/TCAD.2009.2013992

  36. N. Sherwani, Algorithms for VLSI Physical Design Automation (Kluwer Academic, New York, 1999)

    Google Scholar 

  37. H. Veendrick, Nanometer CMOS ICs From Basics to ASICs (Springer, Cham, 2008)

    Google Scholar 

  38. A.B. Kahng, J. Lienig, I.L. Markov, J. Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure (Springer, New York, 2011)

    Google Scholar 

  39. B. Wile, J.C. Goss, W. Roesner, Comprehensive Functional Verification (Morgan Kaufmann, San Francisco, 2005)

    Google Scholar 

  40. N.M. Nayeem, J.E. Rice, A simple approach for designing online testable reversible circuits, in Proceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, BC, 2011, pp. 85–90. https://doi.org/10.1109/PACRIM.2011.6032872

  41. P.K. Lala, An introduction to logic circuit testing. Synth. Lect. Digit. Circ. Syst. 3(1), 1–100 (2008)

    Google Scholar 

  42. M. Abramovici, M.A. Breuer, A.D. Friedman, Design for testability, in Digital Systems Testing and Testable Design, vol. 1 (Wiley-IEEE Press, New York, 1990), pp. 343–419. https://doi.org/10.1109/9780470544389.ch9

  43. A.T. Dahbura, M.U. Uyar, C.W. Yau, An optimal test sequence for the JTAG/IEEE P1149.1 test access port controller, in Test Conference, 1989. Proceedings. Meeting the Tests of Time, International, Washington, DC, 1989, pp. 55–62. https://doi.org/10.1109/TEST.1989.82277

  44. P. Fleming, Semiconductor perspective on test standards, in International Test Conference 1988 Proceeding New Frontiers in Testing, Washington, DC, 1988, pp. 197–198. https://doi.org/10.1109/TEST.1988.207799

  45. C.J. Sherratt, ICL’s first development using IEEE 1149.1 (JTAG), in IEE Colloquium on Application and Development of the Boundary-Scan Standard, London, 1990, pp. 2/1–2/3

    Google Scholar 

  46. IEEE Standard for Test Access Port and Boundary-Scan Architecture, in IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001), May 13 2013, pp. 1–444. https://doi.org/10.1109/IEEESTD.2013.6515989

  47. H. Bhatnagar, Advanced ASIC Chip Synthesis (Kluwer Academic, New York, 2002)

    Google Scholar 

  48. J. Bhasker, R. Chadha, Static Timing Analysis for Nanometer Designs: A Practical Approach, 1st edn. (Springer, New York, 2009)

    Google Scholar 

  49. S. Kilts, Static timing analysis, in Advanced FPGA Design: Architecture, Implementation, and Optimization, vol. 1 (Wiley-IEEE, New York, 2007), pp. 269–278. https://doi.org/10.1002/9780470127896.ch18

  50. W. Wang, V. Reddy, V. Balakrishnan, S. Krishnan, Y. Cao, Statistical prediction of circuit aging under process variations, in Solid State Circuits Technologies, ed. by J.W. Swart (InTech, Croatia, 2010). https://doi.org/10.5772/6875

  51. K. Yelamarthi, C.I.H. Chen, Timing optimization and noise tolerance for dynamic CMOS susceptible to process variations. IEEE Trans. Semicond. Manuf. 25(2), 255–265 (2012). https://doi.org/10.1109/TSM.2012.2185961

  52. M. Alioto, G. Palumbo, M. Pennisi, Understanding the effect of process variations on the delay of static and domino logic. IEEE Trans. Very Large Scale Integr. VLSI Syst. 18(5), 697–710 (2010). https://doi.org/10.1109/TVLSI.2009.2015455

  53. D. Blaauw, K. Chopra, A. Srivastava, L. Scheffer. Statistical timing analysis: from basic principles to state of the art. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4), 589–607 (2008)

    Google Scholar 

  54. A. Chandrakasan, W.J. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits (Wiley, New York, 2000)

    Google Scholar 

  55. Q.K. Zhu, Power Distribution Network Design for VLSI (Wiley-Interscience, New York, 2014)

    Google Scholar 

  56. M. Orshansky, S. Nassif, D. Boning, Design for Manufacturability and Statistical Design: A Constructive Approach, 1st edn. (Springer, New York, 2010)

    Google Scholar 

  57. S. Kalra, Effect of temperature dependence on performance of digital CMOS circuit technologies, in International Conference on Signal Processing and Communication (ICSC), 2013, pp. 392–395

    Google Scholar 

  58. M. Onabajo, J. Silva-Martinez, Analog Circuit Design for Process Variation-Resilient System-on-a-Chip (Springer, New York, 2012)

    Google Scholar 

  59. J. Ma, W. Yang, L. Yang, L. Wu, Z. Liu, On the modeling of process variations and its applications for circuit performance designs, in 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Xi’an, 2012, pp. 1–4. https://doi.org/10.1109/ICSICT.2012.6467638

  60. X. Li, J. Le, L.T. Pileggi, Statistical performance modeling and optimization. Found Trends Electron. Des. Autom. 1(4), 331–480 (2007). http://dx.doi.org/10.1561/1000000008

  61. B. Beacham, P. Hua, C. Lacy, M. Lynch, D. Toffolon, Mixed-signal IP design challenges in 28-nm process and beyond, Synopsys White Paper, July 2012

    Google Scholar 

  62. Y. Cao, L.T. Clark, Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10), 1866–1873 (2007)

    Google Scholar 

  63. R. Radojcic, D. Perry, M. Nakamoto, Design for manufacturability for fabless manufacturers. IEEE Solid-State Circuits Mag. 1(3), 24–33 (2009)

    Google Scholar 

  64. A. Agarwal, D. Blaauw, V. Zolotov, Statistical timing analysis for intra-die process variations with spatial correlation, in IEEE International Conference on Computer Aided Design (ICCAD), November 2003, pp. 900–907

    Google Scholar 

  65. B. Nikolic et al., Technology variability from a design perspective. IEEE Trans. Circuits Syst. Regul. Pap. 58(9), 1996–2009 (2011). https://doi.org/10.1109/TCSI.2011.2165389

  66. A. Gupta, DeepChip, http://deepchip.com/items/0573-03.html. June 2017

  67. T. McConaghy, P. Drennan, Variation-Aware Custom IC Design: Improving PVT and Monte Carlo Analysis for Design Performance and Parametric Yield (Solido Design Automation, Inc., San Jose) (2011)

    Google Scholar 

  68. M. Li, G. Huang, X. Wu et al., A yield-enhanced global optimization methodology for analog circuit based on extreme value theory. Sci. China Inf. Sci. 59, 082401 (2016). https://doi.org/10.1007/s11432-015-0471-4

  69. A. Das, S. Ozdemir, G. Memik, J. Zambreno, A. Choudhary, Microarchitectures for managing chip revenues under process variations. IEEE Comput. Archit. Lett. 7(1), 5–8 (2008)

    Google Scholar 

  70. A. Datta, S. Bhunia, J. H. Choi, S. Mukhopadhyay, K. Roy, Profit aware circuit design under process variations considering speed binning. IEEE Trans. Very Large Scale Integr. VLSI Syst. 16(7), 806–815 (2008). https://doi.org/10.1109/TVLSI.2008.2000364

  71. L.Y.Z. Lin, C.H.P. Wen, Speed binning with high-quality structural patterns from functional timing analysis (FTA), in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macau, 2016, pp. 238–243. https://doi.org/10.1109/ASPDAC.2016.7428017

  72. Q. Shi, M. Tehranipoor, X. Wang, L. Winemberg, On-chip sensor selection for effective speed-binning, in 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), College Station, TX, 2014, pp. 1073–1076. https://doi.org/10.1109/MWSCAS.2014.6908604

  73. P. Das, S.K. Gupta, Extending pre-silicon delay models for post-silicon tasks: validation, diagnosis, delay testing, and speed binning, in 2013 IEEE 31st VLSI Test Symposium (VTS), Berkeley, CA, 2013, pp. 1–6. https://doi.org/10.1109/VTS.2013.6548901

    Google Scholar 

  74. AMD, AMD Processor Pricing, http://www.amd.com/pricing. May 2006

  75. A. Datta, S. Bhunia, J.H. Choi, S. Mukhopadhyay, K. Roy, Speed binning aware design methodology to improve profit under parameter variations, in ASP-DAC ’06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference, 2006, pp. 712–717

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. INAOE, Tonantzintla, Puebla, Mexico

    Victor Champac

  2. Universidad Veracruzana, Xalapa, Veracruz, Mexico

    Jose Garcia Gervacio

Authors
  1. Victor Champac
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jose Garcia Gervacio
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer International Publishing AG, part of Springer Nature

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Champac, V., Garcia Gervacio, J. (2018). Introduction. In: Timing Performance of Nanometer Digital Circuits Under Process Variations. Frontiers in Electronic Testing, vol 39. Springer, Cham. https://doi.org/10.1007/978-3-319-75465-9_1

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-75465-9_1

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-75464-2

  • Online ISBN: 978-3-319-75465-9

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation