Two-Graph Based Semi-topological Analysis of Electronic Circuits with Nullors and Pathological Mirrors

Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 479)

Abstract

Abstraction level elements such as nulattor, norator, current mirrors and voltage mirrors have been very useful in the analysis of linear circuits. In this chapter, we proposed a method for the analysis of linear circuits with the pathological elements which is based on the two-graph representation of these elements and the semi-topological procedure of calculations of the network functions. For completeness, the method has been extended to encompass RLC–elements, all types of controlled sources, voltage and current independent sources. The procedure of calculation is based on the product matrices and on a numerical formula of evaluation of unimodular determinants. No sign rule is required for their evaluations, and canceling terms are extracted during their evaluations. In this chapter the symbolic analysis is preferred because symbolic expressions give good insight on the behavior of the circuit and can also be used in the optimization procedures.

References

  1. 1.
    Soliman AM (2009) Applications of voltage and current unity gain cells in nodal admittance matrix expansion. IEEE Circuits Syst Mag 9(4):29–42MathSciNetCrossRefGoogle Scholar
  2. 2.
    Pierzchala M, Fakhfakh M (2014) Symbolic analysis of nullor-based circuits with the two-graph technique circuits. Syst Signal Process 33(4):1053–1066CrossRefGoogle Scholar
  3. 3.
    Huang W-Ch, Wang H-Y, Cheng P-S, Lin Y-C (2012) Nullor equivalents of active devices for symbolic circuit analysis. Circuits Syst Signal Process 31:865–875MathSciNetCrossRefMATHGoogle Scholar
  4. 4.
    Sánchez-López C (2012) Modeling active devices with nullor for analog signal processing. In: Fakhfakh M, Tlelo-Cuautle E, Fernandez FV (eds) Design of analog circuits through symbolic analysis. Bentham Scientific PublisherGoogle Scholar
  5. 5.
    Tlelo-Cuautle E, Sanchez-Lopez C, Sandoval-Ibarra F (2005) Computing symbolic expressions in analog circuits using nullors. Computacion y Sistemas 9(2):119–132Google Scholar
  6. 6.
    Kumar R, Senani R (2002) Bibliography on nullor and their applications in circuit analysis, synthesis and design. Analog Integr Circuit Signal Process. Kluwer Academic PublicationGoogle Scholar
  7. 7.
    Teleo-Cuautle E, Sarmiento-Reyes LA (2000) Biasing analog circuits using the nullor concept. In: Proceedings of the southwest symposium on mixed-signal design, 2000Google Scholar
  8. 8.
    Haigh DG, Radmore PM (2006) Admittance matrix models for the nullor using limit variables and their application to circuit design. IEEE Trans Circuits Syst I Regul Pap 53(10):2214–2223Google Scholar
  9. 9.
    Martinez-Romero E, Tlelo-Cuautle E, Sánchez-López C, Tan SX-D (2010) Symbolic noise analysis of low voltage amplifiers by using nullors. In: Proceedings of the international workshop on symbolic, modeling of analog circuit design, 2010Google Scholar
  10. 10.
    Tlelo-Cuautle E, Martinez-Romero E, Sánchez-López C, Tan SX-D (2009) Symbolic formulation method for mixed-mode analog circuits using nullors. In: Proceedings of the IEEE international conference on electronics, circuits, and systems, 2009Google Scholar
  11. 11.
    Sanches-Lopez C, Fernandes FV, Tlelo-Cuautle E, Tan SX-D (2011) Patalogical element-based active device models and their applications to symbolic analysis. IEEE Trans Circuits Syst I Regul Pap 58:1382–1395Google Scholar
  12. 12.
    Filaretov V, Gorshkov K (2013) Topological analysis of active networks containing pathological mirror elements. In: Proceedings of the IEEE XXXIII international science conference on electronics and nanotechnology, pp. 460–464Google Scholar
  13. 13.
    Wang H-Y, Huang W-C, Chiang N-H (2010) Symbolic nodal analysis of circuits using pathological elements. IEEE Trans Circuits Syst II Express Briefs 57:874–877CrossRefGoogle Scholar
  14. 14.
    Shi G (2014) Two-graph analysis of pathological equivalent networks. Inter J Circ Theory Appl 43(9):1–20Google Scholar
  15. 15.
    Tlelo-Cuautle E, Sanches-Lopez C, Martinez-Romero E, Tan SX-D (2010) Symbolic analysis of analog circuits containing voltage mirrors and current mirrors. Analog Integr Circuits Signal Process 65(1):89–95Google Scholar
  16. 16.
    Lin P-M (1991) Symbolic network analysis. Elsevier, AmsterdamMATHGoogle Scholar
  17. 17.
    Mayeda W, Seshu S (1965) Generation of trees without duplications. IEEE Trans Circuit Theory CT-12:181–185Google Scholar
  18. 18.
    Pierzchala M, Rodanski B (2004) Two-graph stamps for linear controlled sources. In: The international workshop on symbolic methods and applications to circuit design, Wroclaw, Poland, pp. 41–44Google Scholar
  19. 19.
    Mason SJ, Zimmermann HJ (1956) Electronic circuits, signals, and systems. Willey, New YorkGoogle Scholar
  20. 20.
    Lee BG (1980) The product matrices and new gain formulas. IEEE Trans Circuits Syst CAS-27:284–292Google Scholar
  21. 21.
    Barbay JE, Lago GV, Becker BW (1972) Product graph. In: Proceedings of the 15th midwest symposium circuit theory, May 1972Google Scholar
  22. 22.
    Pierzchala M (1984) Corrected gain formulas. IEEE Trans Circuits Syst CAS-31:581–582Google Scholar
  23. 23.
    Carlin H (1964) Singular network elements. IEEE Trans Circuit Theory 11(1):67–72CrossRefGoogle Scholar
  24. 24.
    Bruton LT (1980) RC-Active circuits: theory and design. Prentice-Hall, New YorkGoogle Scholar
  25. 25.
    Vlach J, Singhal K (1993) Computer methods for circuits analysis and design. Kluwer Academic, NorwelGoogle Scholar
  26. 26.
    Haigh DG (2006) A method of transformation from symbolic transfer function to active-RC circuit by admittance matrix expansion. IEEE Trans Circuits Syst I Regul Pap 53(12):2715–2728Google Scholar
  27. 27.
    Haigh DG, Clarke TJW, Radmore PM (2006) Symbolic framework for linear active circuits based on port equivalence using limit variables. IEEE Trans Circuits Syst I Regul Pap 53(9):2011–2124Google Scholar
  28. 28.
    Sánchez-López C, Fernández FV, Tlelo-Cuautle E, Tan SX-D (2011) Pathological element-based active device models and their application to symbolic analysis. IEEE Trans Circuits Syst I Regul Pap 58(6):1382–1395Google Scholar
  29. 29.
    Sánchez-López C (2013) Pathological equivalents of fully-differential active devices for symbolic nodal analysis. IEEE Trans Circuits Syst I Regul Pap 60(3):603–615Google Scholar
  30. 30.
    Sanchez-Lopez C, Martinez-Romero E, Tlelo-Cuautle E (2011) Symbolic analysis of OTRAs-based circuits. J Appl Res Technol 9(1):69–80Google Scholar
  31. 31.
    Tlelo-Cuautle E, Sanchez-Lopez C, Sandoval-Ibarra F (2005) Computing symbolic expressions in analog circuits using nullors. Comput Sist 9(2):119–132Google Scholar
  32. 32.
    Rodanski B (2002) Extension of the two-graph method for symbolic analysis of circuit with non-admittance elements. In: International workshop on symbolic methods and applications to circuit designGoogle Scholar
  33. 33.
    Awad A, Soliman AM (2002) On the voltage mirrors and current mirrors. Analog Integr Circuits Signal Proccess 32:79–81CrossRefGoogle Scholar
  34. 34.
    Soliman AM (2013) Generation of grounded capacitor minimum component oscilators, Chap 4. In: Tlelo-Cuautle E (ed) Integrated circuits for analog signal processing. SpringerGoogle Scholar
  35. 35.
    Soliman AM (2008) The inverting second generation current conveyor as universal building blocks. Int J Electron Commun 62:114–121CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Wroclaw University of TechnologyWrocławPoland
  2. 2.University of SfaxSfaxTunisia

Personalised recommendations