Advertisement

Keeping up with Real Time

  • Reinhard WilhelmEmail author
  • Jan Reineke
  • Simon Wegener
Chapter

Abstract

This chapter is concerned with timing verification of future avionics software. We critically review a recent CAST position paper, identified as CAST-32A, about certification issues connected to the use of multi-core architectures and show that it leaves several issues unresolved. It introduces robust partitioning as a requirement for the feasibility of timing verification, but fails to precisely define it. We give a precise notion of robust partitioning that guarantees temporal isolation and, therefore, allows for separate timing analysis of tasks running on individual cores. Sometimes, complete temporal isolation is impossible to achieve or will lead to very poor resource allocation. In an ideal setting, one could analyze the timing behavior of a set of applications executed on several cores in a compositional way. We discuss the requirements for a correct analysis of the interference on the shared resources of multi-core processors. Finally, we show how to configure an existing multi-core architecture to enable compositional timing analysis.

References

  1. 1.
    A.C. Shaw, Reasoning about time in higher-level language software. IEEE Trans. Softw. Eng. 15(7), 875–889 (1989).  https://doi.org/10.1109/32.29487
  2. 2.
    C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling, S. Thesing, R. Wilhelm. Reliable and precise WCET determination for a real-life processor, in EMSOFT, vol. 2211, LNCS 2001, pp. 469–485Google Scholar
  3. 3.
    R. Wilhelm, B. Wachter. Abstract interpretation with applications to timing validation, in 20th International Conference on Computer Aided Verification, CAV 2008, Princeton, NJ, USA, 7–14 July 2008, Proceedings ed. by A. Gupta, S. Malik. Lecture Notes in Computer Science, vol. 5123 (Springer, Berlin, 2008), pp. 22–36. ISBN: 978-3-540-70543-7Google Scholar
  4. 4.
    A. Abel, F. Benz, J. Doerfert, B. Dörr, S. Hahn, F. Haupenthal, M. Jacobs, A.H. Moin, J. Reineke, B. Schommer, R.Wilhelm, Impact of resource sharing on performance and performance prediction: a survey, in CONCUR 2013 - Concurrency Theory - 24th International Conference, CONCUR 2013, Buenos Aires, Argentina, 27–30 August 2013, Proceedings. ed. by P.R. D’Argenio, H.C. Melgratti. Lecture Notes in Computer Science, vol. 8052 (Springer, Berlin, 2013), pp. 25–43, ISBN: 978-3-642-40183-1.  https://doi.org/10.1007/978-3-642-40184-8
  5. 5.
    Certification Authorities Software Team (CAST). Position Paper CAST-32A Multi-core Processors, Nov 2016Google Scholar
  6. 6.
    J. Rosen, A. Andrei, P. Eles, Z. Peng, Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip, in 28th IEEE International Real-Time Systems Symposium 2007, pp. 49–60Google Scholar
  7. 7.
    H. Shah, A. Raabe, A, Knoll. Priority division: A high-speed shared memory bus arbitration with bounded latency, in Design, Automation and Test in Europe, DATE 2011, Grenoble, France, 14–18 March 2011, pp. 1497–1500.  https://doi.org/10.1109/DATE.2011.5763319
  8. 8.
    R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell, M. Caccamo, R. Kegley, A predictable execution model for COTS-based embedded systems, in Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium (IEEE Computer Society, Washington, DC, USA 2011), pp. 269–279. ISBN: 978-0-7695-4344-4.  https://doi.org/10.1109/RTAS.2011.33
  9. 9.
    F. Boniol, H. Cassé, E. Noulard, C. Pagetti, Deterministic execution model on COTS hardware, in ARCS, 2012, pp. 98–110Google Scholar
  10. 10.
    A. Hamann, D. Dasari, S. Kramer, M. Pressler, F. Wurst. Communication centric design in complex automotive embedded systems, in 29th Euromicro Conference on Real-Time Systems (ECRTS 2017), ed. by M. Bertogna, vol. 76. Leibniz International Proceedings in Informatics (LIPIcs). Dagstuhl, Germany: Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, 2017, 10:1–10:20. ISBN: 978-3-95977-037-8.  https://doi.org/10.4230/LIPIcs.ECRTS.2017.10. http://drops.dagstuhl.de/opus/volltexte/2017/7162
  11. 11.
    P. Radojković, S. Girbal, A. Grasset, E. Quiñones, S. Yehia, F.J. Cazorla, On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments, ACM Trans. Archit. Code Optim. (2012)Google Scholar
  12. 12.
    Y. Xie, G.H. Loh, PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches, in Proceedings of the 36th Annual International Symposium on Computer Architecture. ISCA ’09 (ACM, Austin, TX, USA, 2009), pp. 174–183, ISBN: 978-1-60558-526-0.  https://doi.org/10.1145/1555754.1555778
  13. 13.
    K.J. Nesbit, J. Laudon, J.E. Smith, Virtual private caches, SIGARCH Comput. Archit. News 35(2), 57–68 (2007), ISSN: 0163-5964.  https://doi.org/10.1145/1273440.1250671
  14. 14.
    M.K. Qureshi, Y.N. Patt, Utility-based cache partitioning: a low- overhead, high-performance, runtime mechanism to partition shared caches, in IEEE/ACM International Symposium on Micro Architecture MICRO ’06 (IEEE Computer Society, 2006), pp. 423–432Google Scholar
  15. 15.
    X. Zhang, S. Dwarkadas, K. Shen, Towards practical page coloring-based multicore cache management, in Proceedings of the 4th ACM European Conference on Computer systems. EuroSys ’09. Nuremberg, (ACM, Germany, 2009), pp. 89–102, ISBN: 978-1-60558-482-9.  https://doi.org/10.1145/1519065.1519076
  16. 16.
    V. Suhendra, T. Mitra, Exploring locking & partitioning for predictable shared caches on multi-cores, in Proceedings of the 45th Annual Design Automation Conference. DAC ’08. Anaheim, (ACM, California 2008), pp. 300–303, ISBN: 978-1-60558-115-6.  https://doi.org/10.1145/1391469.1391545
  17. 17.
    G. Taylor, P. Davies, M. Farmwald, The TLB slice - a low-cost highspeed address translation mechanism. SIGARCH Comput. Archit. News 18.3a 355–363 (1990), ISSN: 0163-5964.  https://doi.org/10.1145/325096.325161
  18. 18.
    J. Reineke, I. Liu, H.D. Patel, S. Kim, E.A. Lee, PRET DRAM controller: bank privatization for predictability and temporal isolation, in Proceedings of the Seventh IEEE/ACM/IFIP International Conference On Hardware/ Software Co design And System Synthesis. CODES+ISSS ’11. (ACM, Taipei, Taiwan, 2011), pp. 99–108, ISBN: 978-1-4503-0715-4.  https://doi.org/10.1145/2039370.2039388
  19. 19.
    H. Yun, R. Mancuso, Z.-P. Wu, R. Pellizzoni, PALLOC: DRAM bank- aware memory allocator for performance isolation on multicore platforms, in Proceedings of Real-Time and Embedded Technology and Application Symp (RTAS), Berlin, Germany, Apr 2014Google Scholar
  20. 20.
    B.D. de Dinechin, D. van Amstel, M. Poulhi‘es, G. Lager, Time-critical computing on a single-chip massively parallel processor, in Design, Automation and Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, 24-28 March 2014. ed. by G. Fettweis, W. Nebel (European Design and Automation Association, 2014), pp. 1–6, ISBN: 978-3-9815370- 2-4.  https://doi.org/10.7873/DATE.2014.110
  21. 21.
    H. Rihani, M. Moy, C. Maiza, R. I. Davis, S. Altmeyer, Response time analysis of synchronous data flow programs on a many-core processor, in Proceedings of the 24th International Conference on Real-Time Networks and Systems, RTNS 2016, Brest, France, 19–21 Oct 2016, pp. 67–76.  https://doi.org/10.1145/2997465.2997472
  22. 22.
    A. Gustavsson, A. Ermedahl, B. Lisper, P. Pettersson, Towards WCET analysis of multicore architectures using UPPAAL, in WCET, ed. By B. Lisper, vol. 15. Dagstuhl, Germany, 2010, pp. 101–112, ISBN: 978-3- 939897-21-7.  https://doi.org/10.4230/OASIcs.WCET.2010.101
  23. 23.
    T. Kelter, P. Marwedel. Parallelism analysis: precise WCET values for complex multi-core systems, in Formal Techniques for Safety-Critical Systems - Third International Workshop, 2014, pp. 142–158Google Scholar
  24. 24.
    T. Kelter, WCET Analysis and Optimization for Multi-Core Real-Time Systems, PhD thesis, TU Dortmund University, 2015Google Scholar
  25. 25.
    S. Schliecker, R. Ernst, Real-time performance analysis of multiprocessor systems with shared memory, ACM Trans. Embed. Comput. Syst. 10(2), 22:1–22:27 (2011)Google Scholar
  26. 26.
    S. Altmeyer, R.I. Davis, L.S. Indrusiak, C. Maiza, V. Nélis, J. Reineke, A generic and compositional framework for multicore response time analysis, in RTNS, pp. 129–138 (2015).  https://doi.org/10.1145/2834848.2834862
  27. 27.
    W.-H. Huang, J.-J. Chen, J. Reineke, MIRROR: symmetric timing analysis for real-time tasks on multicore platforms with shared resources, in DAC, June 2016Google Scholar
  28. 28.
    G.C. Buttazzo, Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications, vol. 23, 2nd edn. (Springer, Real-Time Systems Series, 2004), ISBN 978-0-387-23137-2Google Scholar
  29. 29.
    S. Hahn, M. Jacobs, J. Reineke, Enabling compositionality for multicore timing analysis, in Proceedings of the 24th International Conference on Real Time and Networks Systems (2016).  https://doi.org/10.1145/2997465.2997471, http://embedded.cs.uni-saarland.de/publications/EnablingCompositionalityRTNS2016.pdf
  30. 30.
    T. Lundqvist, P. Stenström, Timing anomalies in dynamically scheduled microprocessors, in RTSS, 1999, pp. 12–21.  https://doi.org/10.1109/REAL.1999.818824
  31. 31.
    S. Hahn, J. Reineke, R. Wilhelm, Toward compact abstractions for processor pipelines, in Correct System Design - Symposium in Honor of Ernst-Rüdiger Olderog on the Occasion of His 60th Birthday, Proceedings. ed. by R. Meyer, A. Platzer, H. Wehrheim, Oldenburg, Germany, 8–9 September 2015, pp. 205–220Google Scholar
  32. 32.
    Infineon Technologies AG. AURIX TC27x D-Step 32-Bit Single-Chip Microcontroller User’s Manual V2.2 2014–12 (2014)Google Scholar
  33. 33.
    R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, C. Ferdinand. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems, IEEE Trans. CAD Integr. Circuits Syst. 28(7) 966–978 (2009).  https://doi.org/10.1109/TCAD.2009.2013287

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  1. 1.AbsInt Angewandte Informatik GmbHSaarbrueckenGermany
  2. 2.Saarland UniversitySaarbrueckenGermany

Personalised recommendations