Abstract
In this chapter, the EPFL substrate model is used to analyze substrate parasitic couplings in high-voltage ICs. With this analysis, circuit performance under substrate current is quickly estimated with SPICE simulations enabling the design of appropriate isolation structures and the optimization of the layout floor plan accordingly. Solutions that most effectively reduce such couplings in a chip are based on the physical separation and the placement of guard rings acting as protections. Such protections are placed between the parasitic injector device and the victims, which are often sensitive analog circuits. A systematic approach to characterize key electrical parameters of guard rings acting as protection is also proposed in this chapter. Finally, a comparative study showing the basic design, the working principle, and the advantages and disadvantages of various protection strategies is presented and compared with already published results.
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Buccella, P., Stefanucci, C., Kayal, M., Sallese, JM. (2018). Substrate Coupling Analysis and Evaluation of Protection Strategies. In: Parasitic Substrate Coupling in High Voltage Integrated Circuits. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-74382-0_7
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DOI: https://doi.org/10.1007/978-3-319-74382-0_7
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