Abstract
The EPFL substrate lumped device models have been coded in VerilogA and validated by comparison with TCAD simulations. The choice of VerilogA implementation allows to simulate the model in standard circuit simulators as the Cadence Spectre used in this chapter. The Synopsys Sentaurus Device simulator will be used as TCAD software for comparison. Since the EPFL modeling methodology is junction based, the characteristics of diodes from low- to high-current regimes are investigated first before addressing the typical configuration of parasitic BJT in an HV ICs. Results are shown for both the lateral parasitic NPN BJT between two wells and the vertical parasitic PNP BJT where DC, AC, transient, and temperature simulations are reported. Finally, breakdown simulations of basic ESD devices are discussed to demonstrate the capability of the model to simulate unstable snapback behaviors.
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Buccella, P., Stefanucci, C., Kayal, M., Sallese, JM. (2018). TCAD Validation of the Model. In: Parasitic Substrate Coupling in High Voltage Integrated Circuits. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-74382-0_4
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DOI: https://doi.org/10.1007/978-3-319-74382-0_4
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