Skip to main content

Integrated Circuit Design and Electromigration

  • Chapter
  • First Online:
Fundamentals of Electromigration-Aware Integrated Circuit Design

Abstract

This chapter describes measures for modifying the present integrated circuit design methodology with the objective of countering electromigration. After introducing the overall design flow (Sect. 3.1) in use today, we explore how analog and digital designs are differentiated, as both areas require different measures to counter electromigration (Sect. 3.2). Understanding that knowledge of the currents flowing in interconnects is a fundamental requisite for an electromigration-aware design flow, we discuss in Sect. 3.3 the different types of currents encountered and show how sensible current values can be determined. Section 3.4 describes how robust current-density boundary values can be determined, using application and reliability specifications provided in mission profiles. Effective current-density verification is at the core of electromigration-aware design flows (Sect. 3.5). In Sect. 3.6, we present options for dealing with problems identified by current-density verification, using layout adjustment techniques. In the final Sect. 3.7, we put forward a number of farther-reaching measures for increasing current-density boundary values, based on our assessment of current technological trends.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 79.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 99.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 129.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    Thermal vias are structurally similar to electrical vias, but serve no electrical purpose. Their primary function is to conduct heat vertically through the chip/die and convey it to the heat sink. A thermal wire is used to spread heat in the lateral direction.

References

  1. J.R. Black, Electromigration—a brief survey and some recent results. IEEE Trans. Electron. Devices 16(4), 338–347 (1969). https://doi.org/10.1109/T-ED.1969.16754

    Article  Google Scholar 

  2. J.R. Black, Electromigration failure modes in aluminum metallization for semiconductor devices. Proc. IEEE 57(9), 1587–1594 (1969). https://doi.org/10.1109/PROC.1969.7340

    Article  Google Scholar 

  3. H.F. Brocke, Finite-Elemente-Analyse von modernen Leitbahnsystemen, Ph.D. thesis, Universität Hannover, 2004

    Google Scholar 

  4. Elmer (2016), https://www.csc.fi/web/elmer, last retrieved on 1 Jan 2018

  5. EIA/JEDEC Publication JEP119A, A Procedure for Executing SWEAT, JEDEC Solid State Technology Association, Aug 2003 [Online]. Available: http://www.jedec.org

  6. EIA/JEDEC Standard JESD61A.01, Isothermal Electromigration Test Procedure, JEDEC Solid State Technology Association, Oct 2007 [Online]. Available: http://www.jedec.org

  7. JEDEC/FSA Joint Publication JP001.01, Foundry Process Qualification Guidelines (Wafer Fabrication Manufacturing Sites), JEDEC Solid State Technology Association, May 2004 [Online]. Available: http://www.jedec.org

  8. G. Jerke, A.B. Kahng, Mission profile aware IC design—a case study, in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE), article no. 64 (2014). https://doi.org/10.7873/date.2014.077

  9. G. Jerke, J. Lienig, Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits. IEEE Trans. CAD Integr. Circ. Syst. 23(1), 80–90 (2004). https://doi.org/10.1109/tcad.2003.819899

    Article  Google Scholar 

  10. G. Jerke, J. Lienig, J. Scheible, Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs, in Proceedings of the 41st Annual Design Automation Conference (2004), pp. 181–184. https://doi.org/10.1145/996566.996618

  11. G. Jerke, J. Lienig, Early-stage determination of current-density criticality in interconnects, in Proceedings of the 11th IEEE International Symposium on Quality Electronic Design (ISQED) (2010), pp. 667–774. https://doi.org/10.1109/isqed.2010.5450505

  12. A.B. Kahng, J. Lienig, I.L. Markov, et al., VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer, ISBN 978-90-481-9590-9, (2011). https://doi.org/10.1007/978-90-481-9591-6

    Chapter  Google Scholar 

  13. A. Krinke, M. Mittag, G. Jerke, et al. Extended constraint management for analog and mixed-signal IC design, in IEEE Proceedings of the 21th European Conference on Circuit Theory and Design (ECCTD) (2013), pp. 1–4. https://doi.org/10.1109/ecctd.2013.6662319

  14. B.K. Liew, N.W. Cheung, C. Hu, Electromigration interconnect lifetime under AC and pulse DC stress, in Proceedings of the 27th International Reliability Physics Symposium (IRPS) (1989), pp. 215–219. https://doi.org/10.1109/relphy.1989.36348

  15. J. Lienig, G. Jerke, Electromigration-aware physical design of integrated circuits, in Proceedings of the 18th International Conference on VLSI Design (2005), pp. 77–82. https://doi.org/10.1109/icvd.2005.88

  16. J. Lienig, Introduction to electromigration-aware physical design, in Proceedings of the 2006 International Symposium on Physical Design (ISPD) (ACM, 2006), pp. 39–46. https://doi.org/10.1145/1123008.1123017

  17. J. Lienig, Electromigration and its impact on physical design in future technologies, in Proceedings of the 2013 ACM International Symposium on Physical Design (ISPD) (ACM, 2013), pp. 33–40. https://doi.org/10.1145/2451916.2451925

  18. J. Lienig, G. Jerke, Current-driven wire planning for electromigration avoidance in analog circuits, in Proceedings of the 2003 Asia and South Pacific Design Automation Conference (ASP-DAC) (2003), pp. 783–788. https://doi.org/10.1109/aspdac.2003.1195125

  19. C.-H. Liu, S.-Y. Kuo, D.T. Lee, et al., Obstacle-avoiding rectilinear Steiner tree construction: a Steiner-Point-Based algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7), 1050–1060 (2012). https://doi.org/10.1109/tcad.2012.2185050

    Article  Google Scholar 

  20. J. Li, H. Miyashita, Post-placement thermal via planning for 3D integrated circuit, in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (2006), pp. 808–811. https://doi.org/10.1109/apccas.2006.342144

  21. J.A. Maiz, Characterization of electromigration under bidirectional (BC) and pulsed unidirectional (PDC) currents, in Proceedings of the 27th International Reliability Physics Symposium (IRPS) (1989), pp. 220–228. https://doi.org/10.1109/relphy.1989.36349

  22. A. Nassaj, J. Lienig, G. Jerke, A new methodology for constraint-driven layout design of analog circuits, in Proceedings of the 16th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2009), pp. 996–999. https://doi.org/10.1109/icecs.2009.5410838

  23. D.G. Pierce, E.S. Snyder, S.E. Swanson, et al., Wafer-level pulsed-DC electromigration response at very high frequencies, in Proceedings of the International Reliability Physics Symposium (RELPHY) (1994), pp. 198–206. https://doi.org/10.1109/relphy.1994.307836

  24. J. Scheible, J. Lienig, Automation of analog IC layout—challenges and solutions, in Proceedings of the International Symposium on Physical Design (ISPD) (ACM, 2015), pp. 33–40. https://doi.org/10.1145/2717764.2717781

  25. W. Wessner, H. Ceric, J. Cervenka, et al., Dynamic mesh adaptation for three-dimensional electromigration simulation, in International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (2005), pp. 147–150. https://doi.org/10.1109/sispad.2005.201494

  26. K. Weide-Zaage, D. Dalleau, X. Yu, Static and dynamic analysis of failure locations and void formation in interconnects due to various migration mechanisms. Mater. Sci. Semicond. Process. 6(1–3), 85–92 (2003). https://doi.org/10.1016/S1369-8001(03)00075-1

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Jens Lienig .

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer International Publishing AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Lienig, J., Thiele, M. (2018). Integrated Circuit Design and Electromigration. In: Fundamentals of Electromigration-Aware Integrated Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-319-73558-0_3

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-73558-0_3

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-73557-3

  • Online ISBN: 978-3-319-73558-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics