Performance Prediction of Acoustic Wave Numerical Kernel on Intel Xeon Phi Processor

  • Víctor MartínezEmail author
  • Matheus Serpa
  • Fabrice Dupros
  • Edson L. Padoin
  • Philippe Navaux
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 796)


Fast and accurate seismic processing workflow is a critical component for oil and gas exploration. In order to understand complex geological structures, the numerical kernels used mainly arise from the discretization of Partial Differential Equations (PDEs) and High Performance Computing methods play a major in seismic imaging. This leads to continuous efforts to adapt the softwares to support the new features of each architecture design and maintain performance level. In this context, predicting the performance on target processors is critical. This is particularly true regarding the high number of parameters to be tuned both at the hardware and the software levels (architectural features, compiler flags, memory policies, multithreading strategies). This paper focuses on the use of Machine Learning to predict the performance of acoustic wave numerical kernel on Intel Xeon Phi many-cores architecture. Low-level hardware counters (e.g. cache-misses and TLB misses) on a limited number of executions are used to build our predictive model. Our results show that performance can be predicted by simulations of hardware counters with high accuracy.


Machine Learning Geophysics applications Many-core systems Performance model 



For computer time, this research partly used the resources of Colfax Research. This work has been granted by Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES), Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq), Fundação de Amparo à Pesquisa do Estado do Rio Grande do Sul (FAPERGS). The authors thank Jairo Panetta from Aeronautics Institute of Technology (ITA) and PETROBRAS oil company for providing the acoustic wave numerical kernel code. It was also supported by Intel Corporation under the Modern Code Project. Research has received funding from the EU H2020 Programme and from MCTI/RNP-Brazil under the HPC4E Project, grant agreement n\(^{\circ }\) 689772. We also thank to RICAP, partially funded by the Ibero-American Program of Science and Technology for Development (CYTED), Ref. 517RT0529.


  1. 1.
    Andreolli, C., Thierry, P., Borges, L., Skinner, G., Yount, C.: Chapter 23 - characterization and optimization methodology applied to stencil computations. In: Reinders, J., Jeffers, J. (eds.) High Performance Parallelism Pearls, pp. 377–396. Morgan Kaufmann, Boston (2015)CrossRefGoogle Scholar
  2. 2.
    Boito, F.Z., Kassick, R.V., Navaux, P.O.A., Denneulin, Y.: Automatic I/O scheduling algorithm selection for parallel file systems. Concur. Comput. Pract. Exp. 28(8), 2457–2472 (2016). cpe. 3606CrossRefGoogle Scholar
  3. 3.
    Caballero, D., Farrés, A., Duran, A., Hanzich, M., Fernández, S., Martorell, X.: Optimizing Fully Anisotropic Elastic Propagation on Intel Xeon Phi Coprocessors. In: 2nd EAGE Workshop on HPC for Upstream (2015)Google Scholar
  4. 4.
    Clapp, R.G.: Seismic processing and the computer revolution(s). SEG Tech. Progr. Expanded Abs. 2015, 4832–4837 (2015)Google Scholar
  5. 5.
    Clapp, R.G., Fu, H., Lindtjorn, O.: Selecting the right hardware for reverse time migration. Lead. Edge 29(1), 48–58 (2010)CrossRefGoogle Scholar
  6. 6.
    Cortes, C., Vapnik, V.: Support-vector networks. Mach. Learn. 20(3), 273–297 (1995)zbMATHGoogle Scholar
  7. 7.
    de la Cruz, R., Araya-Polo, M.: Modeling stencil computations on modern HPC architectures. In: Jarvis, S.A., Wright, S.A., Hammond, S.D. (eds.) PMBS 2014. LNCS, vol. 8966, pp. 149–171. Springer, Cham (2015). Google Scholar
  8. 8.
    Drucker, H., Burges, C.J.C., Kaufman, L., Smola, A., Vapnik, V.: Support vector regression machines. In: Advances in Neural Information Processing Systems, vol. 9, pp. 155–161. MIT Press (1997)Google Scholar
  9. 9.
    Dupros, F., Boulahya, F., Aochi, H., Thierry, P.: Communication-avoiding seismic numerical kernels on multicore processors. In: International Conference on High Performance Computing and Communications (HPCC), pp. 330–335, August 2015Google Scholar
  10. 10.
    Ganapathi, A., Datta, K., Fox, A., Patterson, D.: A case for machine learning to optimize multicore performance. In: Proceedings of the First USENIX Conference on Hot Topics in Parallelism, HotPar 2009, Berkeley, CA, USA , p. 1. USENIX Association (2009)Google Scholar
  11. 11.
    Gonzalez, R.C., Woods, R.E.: Digital Image Processing, 3rd edn. Prentice-Hall Inc., Upper Saddle River, NJ, USA (2006)Google Scholar
  12. 12.
    Kukreja, N., Louboutin, M., Vieira, F., Luporini, F., Lange, M., Gorman, G.: Devito: automated fast finite difference computation. In: Proceedings of the 6th International Workshop on Domain-Specific Languages and High-Level Frameworks for HPC, WOLFHPC 2016, pp. 11–19. IEEE Press (2016)Google Scholar
  13. 13.
    Martínez, V., Dupros, F., Castro, M., Navaux, P.: Performance improvement of stencil computations for multi-core architectures based on machine learning. Procedia Comput. Sci. 108, 305–314 (2017). International Conference on Computational Science, ICCS 2017, Zurich, Switzerland, 12–14 June 2017CrossRefGoogle Scholar
  14. 14.
    Niu, X., Jin, Q., Luk, W., Weston, S.: A self-aware tuning and self-aware evaluation method for finite-difference applications in reconfigurable systems. ACM Trans. Reconf. Technol. Syst. 7(2), 15 (2014)CrossRefGoogle Scholar
  15. 15.
    Rai, J.K., Negi, A., Wankar, R., Nayak, K.D.: On prediction accuracy of machine learning algorithms for characterizing shared L2 cache behavior of programs on multicore processors. In: International Conference on Computational Intelligence, Communication Systems and Networks (CICSYN), pp. 213–219, July 2009Google Scholar
  16. 16.
    Vladuic, D., Cernivec, A., Slivnik, B.: Improving job scheduling in grid environments with use of simple machine learning methods. In: International Conference on Information Technology: New Generations, pp. 177–182, April 2009Google Scholar
  17. 17.
    Weng, L., Liu, C., Gaudiot, J.L.: Scheduling optimization in multicore multithreaded microprocessors through dynamic modeling. In: Proceedings of the ACM International Conference on Computing Frontiers, CF 2013, pp. 5:1–5:10. ACM, New York (2013)Google Scholar

Copyright information

© Springer International Publishing AG 2018

Authors and Affiliations

  • Víctor Martínez
    • 1
    Email author
  • Matheus Serpa
    • 1
  • Fabrice Dupros
    • 2
  • Edson L. Padoin
    • 3
  • Philippe Navaux
    • 1
  1. 1.Informatics Institute (INF)Federal University of Rio Grande do Sul (UFRGS)Porto AlegreBrazil
  2. 2.BRGMOrléansFrance
  3. 3.Regional University of Northwest of Rio Grande do Sul (UNIJUI)IjuíBrazil

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