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Part of the book series: Analog Circuits and Signal Processing ((ACSP))

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Abstract

The phase noise (PN) at the output of the phase locked loop (PLL) sets a fundamental limit to the maximum spectral efficiency that the whole system can achieve. As discussed in Chap. 1, the bit error rate against SNR requirements in an AWGN environment shown in Fig. 1.7 changes drastically when a practical PN profile is considered, see Fig. 1.16. Moreover, together with the tough PN requirements, a PLL should be able to synthesize the necessary LO signal over the whole band of operation.

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Notes

  1. 1.

    It is worth noting that the Colpitts oscillator can be designed to achieve lower phase noise for a given tank Q and supply voltage when compared to a class-C differential LC oscillators (up to \(\approx \)2 dB better). However, this comes at the expenses of a much higher current consumption and lower efficiency [9].

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Vigilante, M., Reynaert, P. (2018). mm-Wave LC VCOs. In: 5G and E-Band Communication Circuits in Deep-Scaled CMOS. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-72646-5_4

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