FPGA-Based Implementation of a Bandwidth Selection Algorithm

Abstract

This chapter discusses author’s own research related to fast computation using the univariate plug-in algorithm, a type of a bandwidth selection algorithm. In contrast to the results presented in Chapter 5, this chapter describes a hardware-based method, which relies on utilizing the so-called field-programmable gate arrays (FPGA). FPGA devices are not often used for purposes of implementing purely numerical algorithms. The proposed implementation can be seen as a preliminary assessment of practical usability of such FPGA-based applications. We describe the notion of a high level synthesis (HLS) approach and then, move on to rewrite the plug-in algorithm in a way ready for a direct FPGA/HLS implementation. This is followed by a description of implementation preliminaries with certain concepts then being described in more detail. The final part of this chapter describes the results confirming the practical usability of FPGA chips for fast implementations of complex numerical algorithms