General Issues of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of Destabilizing Factors
Chapter
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Abstract
Principles of constructing systems for simulating and optimizing digital circuits with consideration of destabilizing factors (DF) are described, including principles of considering the influence of DF on the functioning of digital circuits, construction of models of logic elements, determination of the influence of DF on logic elements, organization of the system for simulating and optimizing digital circuits with consideration of DF. The effectiveness and prospects of this class of systems for simulating and optimizing digital circuits are shown.
References
- 1.Kang S., Leblebici Y., Kim Ch. CMOS Digital Integrated Circuits Analysis & Design. -McGraw-Hill Education; 4 edition, 2014. -736p.Google Scholar
- 2.Mehler R.W. Digital Integrated Circuit Design Using Verilog and Systemverilog. -Newnes; 1 edition, 2014. -448p.Google Scholar
- 3.Kirgizova A.V., Nikiforov A.Y., Grigor’ev N.G., Poljakov I.V., Skorobogatov P.K. Dominant mechanisms of transient-radiation upset in CMOS RAM VLSI circuits realized in SOS technology // Mikroelektronika, Vol. 35, No. 3, 2006. -P. 191-208.Google Scholar
- 4.Messomo E.A. Radiation and Temperature Effects on the APV25 Readout Chip for the CMS Tracker. PhD Dissertation, London University, 2002. -132p.Google Scholar
- 5.Ashok K. Goel. High-Speed VLSI Interconnections. -Wiley India; 2 edition. -2015. -432p.Google Scholar
- 6.
- 7.Lemieux G., Lewis D. Design of Interconnection Networks for Programmable Logic. -Springer; Softcover reprint of the original 1st ed. -2004. -206 p.Google Scholar
- 8.Duan C., LaMeres B.J. On and Off-Chip Crosstalk Avoidance in VLSI Design. -Springer. -2010. -240p.Google Scholar
- 9.Sahoo M., H. Rahaman. Impact of mutual inductance on the crosstalk induced effects in single-walled carbon nanotube bundle interconnects // 31st Symposium on Microelectronics Technology and Devices (SBMicro). -2016. -P. 286-290.Google Scholar
- 10.Zhang X., Jiang W. Impact of crosstalk on signal integrity of high density ceramic package for IC // 17th International Conference on Electronic Packaging Technology (ICEPT). -Paris, 2016. -Vol. 21, No. 12. -P. 429-433.Google Scholar
- 11.Li Ch., Rakhra P., Norman P. Practical computation of di/dt for high-speed protection of DC microgrids // IEEE DC Microgrids (ICDCM). -2017. -Vol. 64, -P. 153-159.Google Scholar
- 12.Zhao S., Roy K., Koh C.K. Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-micron CMOS Circuits // ACM/IEEE International Conference on Computer Aided Design (ICCAD). -San Jose, 2000. -P. 65-72.Google Scholar
- 13.John H. Lau. 3D IC Integration and Packaging // McGraw-Hill Education; 1 edition. -2015. -P. 480Google Scholar
- 14.Vaisband I., Jakushokas R., Popovich M., Mezhiba A., Köse S., Friedman E. On-Chip Power Delivery and Management. -Springer. 2016. -P. 742.Google Scholar
- 15.Tramel R.W., Turowski M., Przekwas A., Schultz J., Frey R.G. Modeling of Electromagnetic Fields in High Speed Electronic Interconnects and Flex Circuit Boards Using a Least Squares FD-TD Algorithm // Fourth International Conference on Modeling and Simulation of Microsystems (MSM). -Hilton Head Island, South Carolina, 2001. -P. 602-605.Google Scholar
- 16.Chumakov A.I., Yanenko A.V., Kalashnikov O.A. RAM radiation functional upsets//Third Workshop on Electronics for LHC Experiments. -London, 1997. -P. 419-425.Google Scholar
- 17.Liden P. On Latching Probability of Particle Induced Transients in Combinational Networks // IEEE International Symposium on Fault Tolerant Computing (FTCS). -Madison, 1994. -P. 340-349.Google Scholar
- 18.Metra C., Favalli M., Ricco B. On-Line Detection of Logic Errors due to Crosstalk, Delay and Transient Faults // IEEE International Test conference. -Washington, 1998. -Vol. 8, No. 4. -P. 844-944.Google Scholar
- 19.Brayton R.K., Sangiovanni-Vincentelli A.L. Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics. -Springer; 2001 edition. 2012. -P. 112.Google Scholar
- 20.Agakhanyan T.M. Mathematical Modeling of Ionizing-Radiation Effects in ICs: A Review // Russian Microelectronics. -2004. -Vol. 33, No. 2. -P. 64-67.Google Scholar
- 21.Lourenco N.E., Fleetwood Z.E., Ildefonso A. The Impact of Technology Scaling on the Single-Event Transient Response of SiGe HBTs // IEEE Transactions on Nuclear Science. -2017. -Vol. 64, Issue: 1. -P. 406-414.Google Scholar
- 22.Celik M., Pileggi L., Odabasioglu A. IC Interconnect Analysis. -Kluwer Academic Publishers, 2002. -320p.Google Scholar
- 23.Hall S.H., Heck H.L. Advanced Signal Integrity for High-Speed Digital Designs. -Wiley-IEEE Press; 1 edition, 2009. -680p.Google Scholar
- 24.Pasricha S., Dutt N. On-Chip Communication Architectures: System on Chip Interconnect (Systems on Silicon). -Morgan Kaufmann, 2008. -544p.Google Scholar
- 25.Nurmi J., Tenhunen H., Isoaho J., Jantcsh A. Interconnect-Centric Design for Advanced SOC and NOC. -Springer, 2010. -460p.Google Scholar
- 26.Theis T.N. The future of interconnection technology // IBM Journal Research and Development, 2000. -Vol. 44, No. 3, -P. 379-390.Google Scholar
- 27.Zarkesh-Ha P., Meindl J.D. Optimum On-Chip Power Distribution Networks for Gigascale Integration (GSI) // International Interconnect Technology Conference (IITC). -Austin, 2001. -P. 125-127.Google Scholar
- 28.Wang X., Zhang D., Su D.. A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits // IEEE Transactions on Very Large Scale Integration (VLSI) Systems. -Anaheim, California, 2016. -Vol. 24, Issue: 5. -P. 1715-1727.Google Scholar
- 29.Wu X., Hong X., Cai Y., Cheng C.K., Gu J., Dai W.M. Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques // ACM/IEEE International Conference on Computer Aided Design (ICCAD). -San Jose, 2001. -P. 153-157.Google Scholar
- 30.Wing-Hung Ki. Power Management Integrated Circuit Analysis and Design. -Wiley-IEEE Press; 1 edition, 2017. -448p.Google Scholar
- 31.Bagad V.S. VLSI Design. Technical Publications; 1 edition, 2011. -288p.Google Scholar
- 32.Ashok B. Mehta. ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies. -Springer, 2017. -328p.Google Scholar
- 33.Boylestad R., Nashelsky L. Electronic Devices and Circuit Theory. -Prentice Hall; 10 edition, 2008. -912p.Google Scholar
- 34.Zhang H., Krooswyk S., Ou J. High Speed Digital Design: Design of High Speed Interconnects and Signaling. -Morgan Kaufmann; 1 edition, 2015. -272p.Google Scholar
- 35.Jespers P., Murmann B. Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables. -Cambridge University Press, 2017. -342p.Google Scholar
- 36.Chen W. Analog and VLSI Circuits. -CRC Press; 3 edition, 2009. -702p.Google Scholar
- 37.Dobkin B., Williams D. Analog Circuit Design: A Tutorial Guide to Applications and Solutions. -Newnes; 1 edition, 2011. -960p.Google Scholar
- 38.Ott H.W.. Electromagnetic Compatibility Engineering. -Wiley; 1st edition, 2009. -872p.Google Scholar
- 39.Guo F., Feng X., Wang Z. Research on Time Domain Characteristics and Mathematical Model of Electromagnetic Radiation Noise Produced by Single Arc // IEEE Transactions on Components, Packaging and Manufacturing Technology. -2017. -Vol. PP, Issue: 99-P. 1-10.Google Scholar
- 40.Chumakov A.I. The effect of cosmic radiation on IC. -Ì.: Radio and communication, 2004. -320p. (in Russian)Google Scholar
- 41.Cherniak M.E., Smolin A.A., Ulanova A.V., Nikiforov A.Y. Investigation of Nonuniform Degradation of CMOS-Sensor Light-Sensitive Surface under Gamma-Irradiation // IEEE Radiation and Its Effects on Components and Systems (RADECS). -2015. -P. 1-3.Google Scholar
- 42.Agakhanyan T.M. Circuit-Design Techniques of Radiation Hardening for Monolithic Op Amps // Russian Microelectronics. -2004. -Vol. 33, No. 3. -P. 183-187.Google Scholar
- 43.Cherniak M., Smolin A., Ulanova A. Investigation of Nonuniform Degradation of CMOS-Sensor Light-Sensitive Surface under Gamma-Irradiation // IEEE Radiation and Its Effects on Components and Systems (RADECS). -2015. -P. 1-3.Google Scholar
- 44.Artamonov A.S., Demidov A.A., Kalashnikov O.A., Nikiforov A.Y., Polevich S.A., Telets V.A. Technique and Results of ADC/DAC Radiation Hardness Simulation Tests//Third Workshop on Electronics for LHC Experiments. -London, 1997. -P. 410-414.Google Scholar
- 45.Kloukinas K. Development of a radiation tolerant 2.0V standard cell library using a commercial deep submicron technology for the LHC experiments // Fourth Workshop on Electronics for LHC Experiments. -Rome, 1998. -P. 574-580.Google Scholar
- 46.Lacoe R. Application of Hardness-By-Design Methodology to Radiation-Tolerant ASIC Technologies // IEEE Transactions on Nuclear Science. -2000. -Vol. 47, No. 6. -P. 2334-2341.Google Scholar
- 47.Agakhanyan T.M., Astvatsaturyan E.P., Skorobogatov P.K. Radiation effects in integrated microcircuits. -Ì.: Enerergoatomizdat, 1989. -256p. (in Russian)Google Scholar
- 48.Korshunov F.P., Bogatirev Yu V., Vavilov V.A. The effect of radiation on integrated microcircuits. -Minsk: Science and Technology, 1986. -254p. (in Russian)Google Scholar
- 49.Chumakov A.I., Egorov A.N., Mavritsky O.B., Yanenko A.V. Evaluation of Moderately Focused Laser Irradiation as a Method for Simulating Single-Event Effects // Russian Microelectronics. -2004. -Vol. 33, No. 2. -P. 106-110.Google Scholar
- 50.Barnaby H.J., Cirba C.R., Schrimpf R.D., Fleetwood D.M., Pease R.L., Shaneyfelt M.R., Turflinger T., Krieg J.F., Maher M.C. Origins of total dose response variability in linear bipolar microcircuits // IEEE Transactions on Nuclear Science. -2000. -Vol. 47, No. 6. -P. 2342-2349..Google Scholar
- 51.Faccio F. Total dose and SEU measurement of test structures in a deep submicron technology // Fourth Workshop on Electronics for LHC Experiments. -Rome, 1998. -P. 114-117.Google Scholar
- 52.Campbell M. A pixel readout chip for 10-30 Mrad in standard 0.25mm CMOS//IEEE Nature Sounds Society (NSS) Symposium. -Toronto, 1998. -P. 823-891.Google Scholar
- 53.Osborn J. Total Dose Hardness of Three Commercial CMOS Microelectronics Foundries // IEEE Transactions on Nuclear Science. -1998. -Vol. 45, No. 3. -P. 1458-1463.Google Scholar
- 54.Holmes-Siedle A., Adams L. Handbook of Radiation Effects. -Oxford University Press, 1993. -218p.Google Scholar
- 55.Snoeys W., Faccio F., Burns M. Layout Techniques to Enhance the Radiation Tolerance of Standard CMOS Technologies Demonstrated on a Pixel Readout Chip // Nuclear Instructions and Methods. -2000. -Vol. 439. -P. 349-360.Google Scholar
- 56.Knoll G.F. Radiation Detection and Measurement. -John Wiley & Sons, 2000. -194p.Google Scholar
- 57.Candelori A., Contarato D., Bacchetta N. High-Energy Ion Irradiation Effects on Thin Oxide p-Channel MOSFETs // IEEE Transactions on Nuclear Science. -2002. -Vol. 49, No. 3. -P. 1364-1371.Google Scholar
- 58.Melikyan V. Logic simulation of digital circuits exposed to radiation // Facta universitatis, series: Electronics and Energetics. -Nis, 1999. -Vol. 12, No. 1. -P. 1-16.Google Scholar
- 59.Melikyan V. Sh., Muradyan V.O. Logic Simulation of radiation behavior of digital circuits // International conference “Computer science and information technologies”. -Yerevan, 2003. -P. 368-398. (in Russian)Google Scholar
- 60.Massengill L.W., Baranski A.E., Van Nort D.O. Analysis of Single-Event Effects in Combinational Logic-Simulation of the AM2901 BitSlice Processor // IEEE Transactions on Nuclear Science. -2000. -Vol. 47, No. 6. -P. 1911-1917.Google Scholar
- 61.Zhu X., Massengill L.W., Cirba C.R. The Effects of Nonphysical Carrier Velocities in High-Gradient Single Event Track Simulations // IEEE Transactions on Nuclear Science. -2000. -Vol. 47, No. 6. -P. 1741-1747.Google Scholar
- 62.Silveira L.M., Devadas S., Reis R.A. VLSI: Systems on a Chip. -Kluwer Academic Publishers, 2000. -696p.Google Scholar
- 63.J. Hurtarte. Understanding Fabless IC Technology. -Newnes; 1 edition, 2007. -296p.Google Scholar
- 64.Bagad V.S. VLSI Technology and Design. -Technical Publications; 1 edition, 2011. -428p.Google Scholar
- 65.M. F. Analog Design for CMOS VLSI Systems. -Kluwer Academic Publishers, 2001. -374p.Google Scholar
- 66.Yeo K.S., Rofail S.S., Goh W.L. CMOS/BiCMOS VLSI: Low Voltage, Low Power. -Prentice Hall, 2002. -624p.Google Scholar
- 67.Pursley D., Yeh T. High-level low-power system design optimization//IEEE VLSI Design, Automation and Test (VLSI-DAT). -2017. -P. 1-4.Google Scholar
- 68.Mishra S., Singh N. System on Chip Interfaces for Low Power Design. -Morgan Kaufmann; 1 edition, 2015. -406p.Google Scholar
- 69.Roy K. Low-Power CMOS VLSI Circuit Design. -John Wiley & Sons Inc, 2003. -320p.Google Scholar
- 70.Flynn D., Aitken R., Gibbons A., Shi K. Low Power Methodology Manual: For System-on-Chip Design. -Springer, 2011. -320p.Google Scholar
- 71.Taur Y., Ning T.H. Fundamentals of Modern VLSI Devices. New York: Cambridge University Press, 1998. -496p.Google Scholar
- 72.Jean Walrand K.B., Zobrist G. Advanced Computer Performance Modeling and Simulation. -CRC Press, 1998. -356p.Google Scholar
- 73.Singh A., Singh R. Electronics Circuit SPICE Simulations with LTspice: A Schematic Based Approach. -CreateSpace Independent Publishing Platform; 1 edition, 2015. -164p.Google Scholar
- 74.Basso Ch. Switch-Mode Power Supplies, SPICE Simulations and Practical Designs. -McGraw-Hill Education; 2 edition, 2014. -992p.Google Scholar
- 75.Guofu N., Shiming Z. Gressler J. Modeling of single-event effects in circuits-hardened high-speed SiGe HBT logic // IEEE Transactions on Nuclear Science. -2001. -Vol. 48, No. 6. -P. 1849-1854.Google Scholar
- 76.Agakhanyan T.M. Integrated Microcircuits. -Ì.: Energoatomizdat, 1983. -464p. (in Russian)Google Scholar
- 77.Alexenko A.G. Fundamentals of microcircuitry. -Ì.: Sov. radio, 1977. -403p. (in Russian)Google Scholar
- 78.Tsividis Y. Mixed Analog-Digital VLSI Devices and Technology. -Kluwer Academic Publishers, 2002. -300p.Google Scholar
- 79.Shagurin I.I. Transistor-transistor Logic Circuits. -Ì.: Sov. radio, 1974. -158p. (in Russian)Google Scholar
- 80.Maniwa T. Focus Report: ASICs Today // Integrated System Design Magazine. -2000. -P. 93-95, 98.Google Scholar
- 81.Razavi B. Design of analog CMOS integrated circuits. -McGraw-Hill Education; 2 edition, 2016. -800p.Google Scholar
- 82.Maloberti F. Analog Design for CMOS VLSI Systems. -Springer, 2010. -388p.Google Scholar
- 83.Baklanov M., Ho P., Zschech E. Advanced Interconnects for ULSI Technology. -Wiley; 1 edition, 2012. -606p.Google Scholar
- 84.Walker M.G. Modeling the wiring of deep submicron IC’s // IEEE Spectrum, -2000. -P. 65-71.Google Scholar
- 85.Goryachev V.A., Zakharov S.M. Transient Analysis of Shielded On-Chip Interconnections // Russian Microelectronics. -2003. -Vol. 32, No. 5. -P. 307-314.Google Scholar
- 86.Goryachev V.A. Effect of Discontinuities on ULSI On-Chip Interconnection Characteristics // Russian Microelectronics. -2002. -Vol. 31, No. 5. -P. 326-334.Google Scholar
- 87.Hong X.L., Zhu Q., Jing T. Non-rectilinear on-chip interconnect-an efficient routing solution with high performance // Chinese Journal of Semiconductors. -2003. -Vol. 24, No. 3. -P. 225-233.Google Scholar
- 88.Xu J., Hong X., Jing T., Zhang L. ETEM: An Efficient Gate and Interconnect Timing Estimator Considering Cross-Coupling for High Performance Layout//IEEE International conference on ASIC (ASICON). -Beijing, China, 2003. -Vol. 1. -P. 254-257.Google Scholar
- 89.Wang X., Yu W., Liu D., Wang Z. Fast extraction of 3-D interconnect resistance: numerical-analytical coupling method // IEEE International conference on ASIC (ASICON). -Beijing, China, 2003. -Vol. 1. -P. 315-318.Google Scholar
- 90.Li T., Wang Z. 2-D interconnect inductance and resistance extraction based on the coupled circuit method // Journal of Computer-Aided Design and Computer Graphics. -2003. -Vol. 15, No. 1. -P. 102-106.Google Scholar
- 91.Wu B. High-bandwidth IC interconnects with silicon interposers and bridges for 3D multi-chip integration and packaging // IEEE Semiconductor Technology International Conference (CSTIC). -2017. -P. 1-3.Google Scholar
- 92.Liu J., Salmela O., Sarkka J., Morris J.E., Tegehall P., Andersson C. Reliability of Microtechnology: Interconnects, Devices and Systems. -Springer, 2011. -204p.Google Scholar
- 93.Kashyap C., Krauter B. A realizable driving point model for on-chip interconnect with inductance // ACM/IEEE 37th Design Automation Conference. -Los Angeles, 2000. -P. 190-195.Google Scholar
- 94.Kleveland Qi X., Yu B.Z. On-chip inductance modeling of VLSI interconnects // International Solid State Circuits Conference (ISSCC). -San Francisco, 2000. -P.172-173.Google Scholar
- 95.Massoud Y., Majors S., Bustami T., White J. Layout techniques for minimizing on-chip interconnect self-inductance // ACM/IEEE 35th Design Automation Conference. -San Francisco, 1998. -P. 566-571.Google Scholar
- 96.Wu B. High-bandwidth IC interconnects with silicon interposers and bridges for 3D multi-chip integration and packaging // IEEE Semiconductor Technology International Conference (CSTIC). -2017. -P. 1-3.Google Scholar
- 97.Dengi E.A., Rohrer R.A. Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect Modeling // ACM/IEEE 34th Design Automation Conference. -Anaheim, California, 1997. -P. 127-132.Google Scholar
- 98.Delorme N., Belliville M., Chilo J. Inductance and capacitance analytic formulas for VLSI interconnects // Electronics letters. -1996. -Vol.32, No. 11. -P. 996-997.Google Scholar
- 99.Melikyan V. Sh., Vatyan A.O. Interconnections model delays for the logic analysis of TTL circuits // SUAB, Vol. 1, Computer Engineering, Moscow, 1997. -P. 189-198. (in Russian)Google Scholar
- 100.Melikyan V. Sh., Vatyan A.O. Interconnections model delays for the logic analysis of ECL circuits // SUAB, Vol. 2, Computer Engineering, Moscow, 1997.-P. 187-194. (in Russian)Google Scholar
- 101.Melikyan V. Sh., Vatyan A.O. Interconnections model delays for the logic analysis of I2L circuits // SUAB, Vol. 3, Computer Engineering, Moscow, 1997. -P. 163-166. (in Russian)Google Scholar
- 102.Melikyan V. Sh., Vatyan A.O., Simonyan A. Sh. Delay models of digital VLSI Interconnects // RAs National Academy of Science and SEUA. Vol. 3, N 3, Yerevan, 1997. -P. 201-205. (in Armenian)Google Scholar
- 103.Melikyan V. Sh., Sargsyan S.M., Petrosyan D.A. Calculation model of parasitic inductances of inner interconnects of VLSI // Simulation, optimization, control, SEUA, Yerevan, Vol. 1, No. 7, 2004. -P. 59-68. (in Russian)Google Scholar
- 104.Melikyan V., Sargsyan S., Petrosyan D. A macromodel of internal interconnects of ICs // RAs National Academy of Science and SEUA. Vol. 57, No. 3, Yerevan, 2004. -P. 506-516. (in Armenian)Google Scholar
- 105.Davis J.A., De V.K., Meindl J.D. A stochastic wire-length distribution for gigascale integration (GSI). – Part I: Derivation and validation // IEEE Transactions on Electron Devices. -1998. -Vol. 45. -P. 580-589.Google Scholar
- 106.Wei H., Wang Z. A weighted average formula for efficient inductance and resistance extraction // IEEE International conference on ASIC (ASICON). -Beijing, China, 2003. -Vol. 1. -P. 996-999.Google Scholar
- 107.Ismail Y.I., Friedman E.G. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits // IEEE Transactions on Very Large Scale Integration (VLSI) Systems. -2000. -Vol. 8. -P. 195-206.Google Scholar
- 108.Rao V.B. Delays analysis of the distributed RC line // ACM/IEEE 32nd Design Automation Conference. -San Francisco, 1995. -Vol. 12, No. 5. -P. 370-375.Google Scholar
- 109.Shepard K.L., Narayanan V., Elmendorf P.C., Cheng G. Global Harmony: Coupled Noise Analysis for Full-Chip RC Interconnect Networks // ACM/IEEE International Conference on Computer Aided Design (ICCAD). -San Jose, 1997. -P. 139-141.Google Scholar
- 110.Zhang L., Jing T., Hong X., Xu J., Xiong J., He L. Performance Optimization Global Routing with RLC Crosstalk Constraints // IEEE International conference on ASIC (ASICON). -Beijing, China, 2003. -Vol. 1. -P. 191-194.Google Scholar
- 111.Chen W.Y., Gupta S.K., Breuer M.A. Test Generation for Crosstalk-Induced Delay in Integrated Circuits // IEEE International Test Conference (ITC). -Washington, 1999. -P. 191-200.Google Scholar
- 112.Gupta A. Crosstalk noise and delay analysis for high speed on-chip global RLC VLSI interconnects with mutual inductance using 90nm process technology // IEEE Computing, Communication & Automation (ICCCA). -2015. -P. 1215-1219.Google Scholar
- 113.Caddemi A., Cardillo E.. A study on dynamic threshold for the crosstalk reduction in frequency-modulated radars // IEEE Computing and Electromagnetics International Workshop (CEM). -2017. -P. 29-30.Google Scholar
- 114.Khatri S.P., Brayton R.K., Sangiovanni-Vincentelli A.L. Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics. -Kluwer Academic Publishers, 2001. -144p.Google Scholar
- 115.Xu J., Hong X., Jing T., Cai Y., Gu J. A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design // IEEE Asia and South Pacific Design Automation Conference. -Kitakyushu, Japan, 2003. -Vol. E86-A, No. 12. -P. 847-850.Google Scholar
- 116.Servel G., Huret F., Paleczny E. Inductance Effect in Interconnect Coupling Noise // IEEE 5th Workshop on signal propagation on Interconnects. -Venice, 2001. -P. 74-81.Google Scholar
- 117.Archambeault B. PCB Design for Real-World Emi Control. -Kluwer Academic Publishers, 2002. -244p.Google Scholar
- 118.John H. Lau. 3D IC Integration and Packaging. -McGraw-Hill Education; 1 edition, 2015. -480p.Google Scholar
- 119.Xiao H. 3D IC Devices, Technologies, and Manufacturing. -The International Society for Optical Engineering, 2016. -P. 220p.Google Scholar
- 120.Kuo J., Su K. CMOS VLSI Engineering: Silicon-on-Insulator (SOI). -Springer, 2010. -460p.Google Scholar
- 121.Amaru L. New Data Structures and Algorithms for Logic Synthesis and Verification. -Springer; 2017, -156p.Google Scholar
- 122.Qiu M., Li J. Real-Time Embedded Systems: Optimization, Synthesis, and Networking. -CRS Press; 1 edition, 2011. -231p.Google Scholar
- 123.Roth Ch.H., Kinney L. Fundamentals of Logic Design. -CL-Engineering; 6 edition, 2009. -784p.Google Scholar
- 124.Semiconductor Industry Association. The National Technology Roadmap for Semiconductors (SIA 2015). -62p.Google Scholar
- 125.The International Technology Roadmap for Semiconductors. -2016. -75p.Google Scholar
- 126.Semiconductor Industry Association. The National Technology Roadmap for Semiconductors (SIA 2014). -40p.Google Scholar
- 127.Restle P., Ruehli A., Walker S.G. Dealing with inductance in high-speed chip design // ACM/IEEE 36th Design Automation Conference. -New Orleans, 1999. -P. 904-909.Google Scholar
- 128.Hong X.L., Jing T., Xu J.Y., Bao H.Y., Gu J. CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing // Journal of Computer Science and Technology (JCST). -2003. -Vol. 18, No. 6. -P. 732-738.Google Scholar
- 129.Bubennikov A., Blinnik S. Design and Optimization of Super-Speed CMOS. CBiCMOS Circuits Based on TCAD and Time-Logical Simulator // Baltic Electronics Conference (BEC). -Tallin, 1996. -P. 256-261.
- 130.Melikyan V.Sh., Nazinyan S.M. Optimization algorithm of digital paths delays // Proceedings of “Computer Science and Information technologies” International Conference, Yerevan, 1997. -P. 322-325. (in Armenian)Google Scholar
- 131.Melikyan V.Sh., Hovhannisyan D.D. Delay minimization algorithm of critical paths of digital circuits // RAs National Academy of Science and SEUA. Vol. 57, No. 2, Yerevan, 2004. -P. 324-330. (in Russian)Google Scholar
- 132.Wunder B., Lehmann G., Muller-Glaser K.D. VAMP: a VHDL based concept for accurate modeling and post layout timing simulation of electronic systems. // ACM/IEEE 33rd Design Automation Conference. -Las Vegas, 1996. -P. 119-124.Google Scholar
- 133.Liou J.J., Wang L.C., Cheng K.T. On Theoretical and Practical Considerations of Path Selection for Delay Fault Testing // ACM/IEEE International Conference on Computer Aided Design (ICCAD). -Freiberg, 2002. -P. 94-100.Google Scholar
- 134.Chen H.C., Du D.H., Liu L.R. Critical Path Selection for Performance Optimization // IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. -1993. -Vol. 12, No. 2. -P. 185-195.Google Scholar
- 135.Graziano M., Delaurenti M., Masera G., Piccinini G., Zamboni M. Noise Safety Design Methodologies // IEEE International Symposium on Quality Electronic Design (ISQED). -Arlington, 2000. -P. 157-166.Google Scholar
- 136.Melikyan V.Sh., Hovasapyan N.O., Manukyan G.G. Definition of noise immunity of digital VLSI//Interuniversity proceedings of YPI “Technical means and mathematical provision of computing systems”, Yerevan, 1988. -P. 60-62. (in Russian)Google Scholar
- 137.Fu J., Hong X., Cai Y., Luo Z. Decoupling Capacitor Allocation for Power Delivery Network Noise Reduction Based on Standard Cell Layouts // IEEE International conference on ASIC(ASICON). -Beijing, China, 2003. -Vol. 1. -P. 101-104.Google Scholar
- 138.Liou J.J., Krstic A., Jiang Y.M., Cheng K.T. Modeling, Testing and Analysis for Delay Defects and Noise Effects in Deep Submicron Devices // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. -2003. -Vol. 22, No. 6. -P. 756-769.Google Scholar
- 139.Melikyan V., Sargsyan S. A simulation method of considering parasitic effects of supply buses of ICs // Information Technologies and Management. Vol. 1, Yerevan, 2004. -P. 34-48. (in Armenian)Google Scholar
- 140.Sotiriadis P., Chandrakasan A. Reducing bus delay in sub-micron technology using coding // IEEE Asia and South Pacific Design Automation Conference. -Japan, Yokohama, 2001. -P. 109-114.Google Scholar
- 141.Kleveland B., Qi X., Madden L. Line inductance extraction and modeling in real chip with power grid // International Electron Devices Meeting. -1999. -P. 901-904.Google Scholar
- 142.Saleh R., Hussain Z., Rochel S., Overhauser D. Clock Verification in the Presence of IR-drop in the Power Distribution Network // IEEE Transaction on CAD of IC and Systems. -2000. -Vol. 19, No. 6. -P. 635-644.Google Scholar
- 143.Aragones X., Gonzales J., Rubio A. Analysis and Solutions for switching Noise Coupling in Mixed-Signal ICs. -Kluwer Academic Publishers, 1999. -236p.Google Scholar
- 144.Charbon E., Gharpurey R., Miliozzi P., Meyer R.G., Sangiovanni-Vincentelli A.L. Substrate Noise Analysis and Optimization for IC Design. -Kluwer Academic Publishers, 2001. -200p.Google Scholar
- 145.Van Heijningen M., Compiet J., Wambacq P., Donnay S., Engels M., Bolsens L. Analysis and Experimental Verification of Digital Substrate Noise Generation for Epi-Type Substrates // IEEE Journal Solid-State Circuits. -2000. -Vol. 35. -P. 1002-1008.Google Scholar
- 146.Panda R., Blaauw D., Chaudry R., Zolotov V., Young B., Ramaraju R. Model and Analysis for Combined Package and On-Chip Power Grid Simulation // International Symposium on Low Power Electronics and Design (ISLPED). -Huntington Beach, California, 2000. -P. 179-184.Google Scholar
- 147.Bondyopadhyay P.K. Moore’s law governs the silicon revolution // Proceedings of the IEEE. -1998. -Vol. 86, No. 1. -P. 78-81.Google Scholar
- 148.Burger D., Goodman J.R. Billion-transistor architectures // Proceedings of the IEEE Computer. -1997. -Vol. 30, No. 9. -P. 46-48.Google Scholar
- 149.Norenkov I.P. Automated design basics. -M.: MNTU after N.E. Bauman, 2002. -336p. (in Russian)Google Scholar
- 150.Zobrist G., Leonard J.V. Simulation Systems. -CRC Press, 2000. -324p.Google Scholar
- 151.Hatchel G.D., Sangiovanni-Vincentelli A. A Survey of Third Generation Simulation Techniques // Proceedings of the IEEE. -1981. -Vol. 69, No. 10. -P. 1264-1280.Google Scholar
- 152.Barmakov Yu N., Bakharov V.A., Ilyin V.N. et al. Research results for a range of electronic circuit analysis programs // Proc. of USSR universities. Radioelectronics. -1981. N 6. -P. 27-37. (in Russian)Google Scholar
- 153.Newton A.R. Computer-aided design of superintegrated integrated circuits//Works of TIIER. -1981. -T.69, N10. -P. 7-20.Google Scholar
- 154.Farrahi A.H., Hathaway D.J., Wang M., Sarrafzadeh M. Quality of EDA CAD Tools: Definitions, Metrics and Directions // 1st International Symposium on Quality of Electronic Design. -San Jose, 2000. -P. 395-403.Google Scholar
- 155.Breuer M.A. Latest achievements in design automation and analysis of digital circuits//In book: Automation in Design/under editorship of D. Kalakhan and others. ‑M.: Mir, 1972. -P. 19-47. (in Russian)Google Scholar
- 156.Batalov B.V., Egorov Yu. B., Rusakov S.G. Mathematical modeling basics of VLSI on PCs. -M.: Radio i svyaz, 1982. -168p. (in Russian)Google Scholar
- 157.Jr. Roth, L. John. Digital Systems Design Using VHDL.-CL. Engineering; 3 edition, 2017. -628p.Google Scholar
- 158.Clietti M. Advanced Digital Design with The Verilog Hdl. -Pearson India, 2017. -992p.Google Scholar
- 159.Abraitis L.B., Sheynauskas R.I., Jilevichyus V.A. Computer-aided design. -M.: Sov. Radio, 1978. -272p. (in Russian)Google Scholar
- 160.Budulin S.S., Barmaulov Yu M., Berdishyev V.A. Automated design of digital circuits. -M.: Radio i svyaz, 1981. -240p. (in Russian)Google Scholar
- 161.Waterman S. Digital Logic Simulation and CPLD Programming with VHDL. -Prentice Hall, 2003. -301p.Google Scholar
- 162.Nguyen Q., Van Le T. Time-parameterized Temporal Logic-based Framework for Discrete-Event Simulation // 9th International Symposium on Languages for Intensional Programming. -Aachen, 1996. -Vol. 11, No. 8. -P. 43-51.Google Scholar
- 163.Avril H., Tropper C. Scalable Clustered Time Warp and Logic Simulation // VLSI Design. -1999. -Vol. 9, No. 3. -P. 36-42.Google Scholar
- 164.Kim H., Jean J. Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation // VLSI Design. -1999. -Vol. 9, No. 3. -P. 23-29.Google Scholar
- 165.Melikyan V.Sh. Logic simulation algorithm of digital circuits with consideration of environment temperature // Proceedings of 3rd International scientific-technical conference “Innovative Information Technologies and Systems”, Penza, 1998. -P. 158-160. (in Russian)Google Scholar
- 166.Melikyan V.Sh. Logic simulation of digital circuits with consideration of destabilizing factors // Proceedings of the 5th International Conference on The Experience of Designing and Application of CAD Systems in Microelectronics (CADSM’99), Lvov, 1999. -P. 142-144. (in Russian)Google Scholar
- 167.Melikyan V., Poghosyan A., Durgaryan A., Petrosyan H., Simonyan M. Method of Parametrical Optimization of Multi-Core Processors // Proceedings of the 31st International Scientific-Technical Conference on “Electronics and Nanotechnologies”, Kiev, Ukraine, 2011. -P. 126-130. (in Russian)Google Scholar
- 168.Melikyan V.Sh., Simonyan A.Sh. Consideration of external affects in the program of logic analysis // Interuniversity proceedings of YPI “Technical means and mathematical provision of computing systems”, Yerevan, 1990. -P. 61-64. (in Russian)Google Scholar
- 169.Melikyan V.Sh. Principles of logic simulation of digital circuits with consideration of destabilizing factors // Proceedings of “Computer Science and Information Technologies” International Conference, Yerevan, 1999. -389-393. (in Russian)Google Scholar
- 170.Melikyan V.Sh., Balagezyan A.R. Key design tools of logic macromodels of digital circuits // Proceedings of “Computer Science and Information Technologies” International Conference, Yerevan, 1999. -P. 394-398. (in Russian)Google Scholar
- 171.Heydemann M.H. A survey of MOS logic simulation tools // 9th European Solid-State Circuits Conference. -Lausanne, 1983. -P. 19-24.Google Scholar
- 172.Levin V.I. Dynamics of Logical devices and systems. -M.: Energy, 1980. -224p. (in Russian)Google Scholar
- 173.Zolotorevich L.A. Delay-Conscious Switch-Level Modeling of MOS LSI Circuits // Russian Microelectronics. -2003. -Vol. 32, No. 3. -P. 182-188.Google Scholar
- 174.Melikyan V.Sh., Ovasapyan N.O., Petrukhin V.P. United system of logic simulation and layout design of VLSI // Automation design in electronics, “Technics”, Vol. 40, Kiev, 1989. -P. 61-64. (in Russian)Google Scholar
- 175.Melikyan V., Soghomonyan V., Mkrtchyan E. Model of digital cells’ states in algorithmic calculation//Interuniversity scientific and methodical proceedings. 6.51. Yerevan, 2003. -P. 44-54. (in Armenian)Google Scholar
- 176.Melikyan V., Kulakhszyan A. Logic models with consideration of leakage delays, quantum and averaged states // Information technologies and management. Vol. 3, Yerevan, 2003. -P. 8-15. (in Armenian)Google Scholar
- 177.Melikyan V., Kulakhszyan A. Logic models with averaged states // RAs National Academy of Science and SEUA, Yerevan, RA, Vol. 56, No. 3, Yerevan, 2003. -P. 491-499. (in Armenian)Google Scholar
- 178.Lu S.K., Chen J.L., Wu C.W., Chang W.F., Huang S.Y. Combinational circuit fault diagnosis using logic emulation // IEEE International Symposium on Circuits and Systems (ISCAS). -Bangkok, 2003. -Vol. 5. -P. 549-552.Google Scholar
- 179.Schittenkopf Ch., Deco G., Brauer W. Finit Automata-Models for the Investigation of Dynamical Systems // Information Processing Letters. -1997. -Vol.63, No. 3. -P. 137-141.Google Scholar
- 180.Snubald R., Svensson C. Accurate CMOS Models for Event driven logic simulators // European Conference on Circuit Theory and Design (ECCTD). -Stutgard, 1985. -P. 483-485.Google Scholar
- 181.Wang Z., Maurel P.M. LECSIM: A levelized event driven compiled logic simulator // ACM/IEEE 27th Design Automation Conference. -Orlando, Florida, 1990. -P. 491-496.Google Scholar
- 182.Hayes J.P. Digital Simulation with multiple logic values // IEEE Transaction on CAD. -1986. -Vol. 5, No. 2. -P. 274-283.Google Scholar
- 183.Flake P.L., Moorby P.R., Musgrave G. An Algebra for Logic Strength Simulation // ACM/IEEE 20th Design Automation Conference. -1983. -P. 615-618.Google Scholar
- 184.Herout A., Szanto L. Logic Simulator Based on Resistor Nets // 7th European Conference on Circuit Theory and Design (ECCTD). -Prague, 1985. -P. 149-152.Google Scholar
- 185.Keller J., Rauber T., Rederlechner B. Scalability Analysis for Conservative Simulation of Logical Circuits // VLSI Design. -1999. -Vol. 9, No. 3. -P. 8-15.Google Scholar
- 186.Miszo A. Digital logic testing and simulation. -New York: John Wiley and Sons, 1987. -285p.Google Scholar
- 187.Bailay M.L., Briner J.V., Chamberlain R.D. Parallel logic simulation of VLSI systems // ACM Computing Surveys. -1994. -Vol. 26, No. 3. -P. 255-294.Google Scholar
- 188.Steinman J. SPEEDES: A multiple synchronization environment for parallel discrete-event simulation // Journal on Computer Simulation. -1992. Vol. 2. -P. 251-286.Google Scholar
- 189.Chamberlain R.D. Parallel logic simulation of VLSI systems // ACM/IEEE 32nd Design Automation Conference. -San Francisco, 1995. -P. 139-143.Google Scholar
- 190.Ferscha A. Parallel and distributed simulation of discrete event systems // Parallel and Distributed Computing Handbook. -McGraw-Hill, 1995. -P. 666-673.Google Scholar
- 191.Naroska E. Parallel VHDL simulation // ACM/IEEE Conference Design, Automation and Test in Europe (DATE). -Paris, 1998. -P. 159.Google Scholar
- 192.Longeann D., Richard Shi C.J. Distributed simulation of VLSI circuits via lookahead-free self-adaptive optimistic and conservative synchronization // ACM/IEEE International Conference on Computer Aided Design (ICCAD). -San Jose, 1998. -P. 362.Google Scholar
- 193.Walker P.A., Ghosh S. Asynchronous, distributed event driven simulation algorithm for execution of VHDL on parallel processors // ACM/IEEE 32nd Design Automation Conference. -San Francisco, 1995. -P. 144.Google Scholar
- 194.Noble B.L., Chamberlain R.D. Performance of Speculative Computation in Synchronous Parallel Discrete-Event Simulation on Multiuser Execution Platforms // 8th IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS). -Chicago, 1996. -P. 489-494.Google Scholar
- 195.Noble B.L., Peterson G.D., Chamberlain R.D. Performance of Synchronous Parallel Discrete-event Simulation // 28th International Conference on System Sciences. -Waileau Maui, 1995. -Vol. 2. -P. 185-186.Google Scholar
- 196.Noble B.L., Wade J.C., Chamberlain R.D. Performance Predictions for Speculative, Syschronous, VLSI Logic Simulation // 34th Annual Simulation Symposium. -Waileau Maui, 2001. -P. 56-64.Google Scholar
- 197.Chen Y., Noble B.L., Chamberlain R.D. Comparing Edge-cuts to Communications Volume in Parallel VLSI Logic Simulation // 8th IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS). -Chicago, 1996. -P. 481-484.Google Scholar
- 198.Luksch P. Evaluation of three approaches to parallel logic simulation on a distributed memory multiprocessor // 26th Annual Simulation Symposium. -Arlington, 1993. -P. 2-11.Google Scholar
- 199.Lewis D. M. A hierarchical compiled code event-driven logic simulator // IEEE Transaction Computer-Aided Design. -1991. -Vol. 10. -P. 726-737.Google Scholar
- 200.Melikyan V.Sh. A logic simulation method for reproduction of signal bumps in interconnects // Manual of Engineering Academy of Armenia. Vol. 1, No. 3, Yerevan, 2004. -P. 449-451. (in Russian)Google Scholar
- 203.Arkhangelskiy A.Y., Arkhangelskaya I.T., Gribkova E.M., Levshin N.G., Melikyan V.Sh., Savinova T.A., Sergienko V.Y. Design automation of electronic circuits / under the editorship of T.M Akhakhanyan. -M.: MEPhI, 1985. -92p. (in Russian)Google Scholar
- 204.Ogrodzki J. Circuit Simulation Methods and Algorithms. -CRC Press, 1994. -342p.Google Scholar
- 205.Arkhangelskiy A.Y., Levshin N.G., Svetsov S.V. Complex of programs of electrical analysis of electronic devices ELAIS.-J.: MEPhI, 1982. -90p. (in Russian)Google Scholar
- 206.Valtonen M. APLAC-Object-Oriented Circuit Simulation and Design Tool // IEEE Microwaves and RF Conference. -London, 1997. -P. 245-250.Google Scholar
- 207.Abramov I.I., Goncharenko I.A., Ignatenko S.A., Korolev A.V., Novik E.G., Rogachev A.I. Nanodev: A Nanoelectronic-Device Simulation Software System // Russian Microelectronics. -2003. -Vol. 32, No. 2. -P. 97-104.Google Scholar
- 208.S. Li, Y. Fu. 3D TCAD Simulation for Semiconductor Processes, Devices and Optoelectronics. -Springer; 2016. -308p.Google Scholar
- 209.Bubennikov A.N., Sadovnikov A.D. Physical-technological design of bipolar elements in silicon ICs. -M.: Radio i svyaz, 1991. -288p. (in Russian)Google Scholar
- 210.Abramov I.I. Simulation of physical processes in silicon integral microcircuit elements. -BSU, 1999. -89p. (in Russian).Google Scholar
- 211.Litovski V., Zwolinski M. VLSI Circuit Simulation and Optimization. -Kluwer Academic Publishers, 1996. -368p.Google Scholar
- 212.Grivet Talocia S., Stievano I.S., Maio I.A., Canavero F.G. Combined FDTD macromodel simulation of interconnected digital devices // ACM/IEEE Conference Design, Automation and Test in Europe (DATE). -Munich, 2003. -P. 536-541.Google Scholar
- 213.Forzan C., Franzini B., Guardiani C. Accurate and Efficient Macromodel of Submicron Digital Standard Cells//ACM/IEEE 34th Design Automation Conference. -Anaheim, California, 1997. -Vol. 15, No. 3. -P. 356-361.Google Scholar
- 214.Stievano S., Chen Z., Becker D., Canavero F.G., Katopis G., Maio I.A. Macromodeling of Digital I/O Ports for System EMC Assessment // ACM/IEEE Conference Design, Automation and Test in Europe (DATE). -Paris, 2002. -P. 1044-1049.Google Scholar
- 215.Odabasioglu A., Celik M., Pileggi L.T. PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm // ACM/IEEE 34th Design Automation Conference. -Anaheim, California, 1997. -P. 58-65.Google Scholar
- 216.Kong J.T., Overbauser D. Methods to improve digital MOS macromodel accuracy // IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems. -1995. -Vol. 14, No. 7. -P. 868-881.Google Scholar
- 217.Petkovic P., Litovski V. Macromodeling and macroanalysis of CMOS LSI electronic circuits // The first International Conference on Computer Technology, Systems and Applications. -Hamburg, 1987. -P. 512-513.Google Scholar
- 218.Dartu F., Tutuianu B., Pileggi L.T. RC-Interconnect Macromodels for Timing Simulation // ACM/IEEE 33rd Design Automation Conference. -Las Vegas, 1996. -P. 611-616.Google Scholar
- 219.Melikyan V.Sh., Arkhangelskiy A.Y. Macromodels on switched capacitors elements // Radioelectronics. Vol. 29, No. 6, 1986. -P. 86-87. (in Russian)Google Scholar
- 220.Melikyan V.Sh. Macromodel of logic gate-chains//Simulation, optimization, control, State Engineering University of Armenia, Yerevan, Armenia, Vol. 2, Yerevan, 1998. -P. 52-57. (in Armenian)Google Scholar
- 221.Arkhangelsky A., Svettsov S. Methodology of synthesis of electric macromodels of logic circuits of medium and large integration levels // Computer-aided design in electronics. -Kiev, 1980. -T.22. P. 64-70, (in Russian)Google Scholar
- 222.Flexer L.A., Tumanov V.S. Analysis of complex circuits by macrosimulation method//News of higher educational institutions of the USSR. Radio electronics. -1983. -T.26, N 6. -P. 81-83 (in Russian).Google Scholar
- 223.Baghov V.A. Macrosimulation of digital and pulse circuits using macro elements // News of higher educational institutions of the USSR. Radio electronics. -1980. -N 6. -P. 13-20. (in Russian)Google Scholar
- 224.Greenbaum J.R. Digital-IC models for computer aided design // Electronics. -1973. -Vol. 46, No. 25. -P. 154-175.Google Scholar
- 225.Li X., Li P., Xu Y., Pileggi L.T. Analog and RF Circuit Macromodels for System-Level Analysis // ACM/IEEE 41th Design Automation Conference. -Anaheim, California 2003. -P. 478-483.Google Scholar
- 226.Bogliolo A., Benini L. Robust RTL Power Macromodels // IEEE Transactions On Very Large Scale Integration (VLSI) Systems. -1998. -Vol. 6, No. 4. -P. 578-581.Google Scholar
- 227.Arkhangelskiy A.Y. Mixed-Mode Simulation of VLSI.-Kiev: Znanie, 1985. -24p. (in Russian)Google Scholar
- 228.Melikyan V. Structural and eventual decomposition of large electronic schemes // Trans black sea region symposium on applied electromagnetism. -Athens, 1996. -P. MMWS 7.Google Scholar
- 229.Melikyan V., Mkrtchyan E., Mkrtchyan K., Hovhannisyan D., Soghomonyan V. Isolation methods of electronic circuits // RAs National Academy of Science and SEUA, Vol. 57, No 1, Yerevan, 2004. -P. 130-137. (in Armenian)Google Scholar
- 230.De Man H.J., Newton A.R. Hybrid Simulation // IEEE International Symposium on Circuits and Systems (ISCAS). -Tokyo, Japan, 1979. -P. 249-259.Google Scholar
- 231.Reynaert Ph., De Man H., Arnout Y., Cornelissen J. DIANA: A Mixed-Mode Simulator with a Hardware Description Language for Hierarchical Design of VLSI // IEEE International Conference on Circuits and Computers. -New York, 1980. -P. 356-360.Google Scholar
- 232.Saleh R.A., Newton A.R. Mixed-mode Simulation. -Kluwer Academic Publishers, 1990. -248p.Google Scholar
- 233.De Man H.J. Mixed-Mode Simulation for MOS-VLSI Why, Where and How? // IEEE International Symposium on Circuits and Systems (ISCAS). -Rome, Italy, 1982. -P. 699-701.Google Scholar
- 234.Maniwa R. Analog and Mixed-Signal Simulation Tools//Integrated System Design. -1996. -Vol. 2, No. 3. -P. 58-64.Google Scholar
- 235.Melikyan V.Sh. Logic-circuit simulation of analog-digital nodes of radio metering devices // Proceedings of 9th All-Union Scientific-Technical Conference of “Radio metering”, Kaunas, 1983. -P. 177-180. (in Russian)Google Scholar
- 236.Arkhangelskiy A.Y. Lavrenov O.E., Rojukalns P.P., Melikyan V. Sh., Svettsov S.V., Fedorkov B.G. A program of mixed-mode simulation of analog-digital VLSI//Theses of reports of All-Union Conference of “Methods and microelectronic means of digital conversion and signal processing”, Riga, 1983. -P. 231-236. (in Russian)Google Scholar
- 237.Arkhangelskiy A.Y., Melikyan V.Sh. Functionality models of logic cells in the program of mixed-mode logic-circuit simulation // Theses of reports of All-Union Scientific-Technical Conference of “Design Automation of Computers and Systems”, Yerevan, 1983. -P. 80-82. (in Russian)Google Scholar
- 238.Melikyan V.Sh., Arkhangelskiy A.Y. Mixed-mode circuit and logic simulation of analog digital circuits // Electronic simulation, Vol. 6, N5, Kiev, Ukraine, 1984. -P. 35-39. (in Russian)Google Scholar
- 239.Arkhangelskiy A.Y., Melikyan V.Sh., Levshin N.G. Principles of designing a system of mixed-mode simulation of electronic circuits // Seminar materials of “Design Automation in radioelectronics and electrical engineering”, Moscow, 1984. -P. 91-93. (in Russian)Google Scholar
- 240.Arkhangelskiy A.Y., Melikyan V.Sh. A program of mixed-mode analysis of analog-digital circuits // Proceedings of “Electrical engineering and devices for experimental physics”, Moscow, 1985. -P. 134-138. (in Russian)Google Scholar
- 241.Bandarenko V.M., Aghmetov B.S., Bilenko V.I. Application of hermitian splines in the numerical realization of logic-electric macromodels // Proceedings of AN USSR. Series “A”, Physical-mathematical and technical sciences. -1983. -N 6. -P. 49-52. (in Russian)Google Scholar
- 242.Martinyuk V.A., Fedoruk V.G. Logic-electrical analysis algorithm of VLSI // Theses of reports of All-Union Scientific-Technical Conference of. “Automation of design PC and systems”. -Yerevan, 1983. -P. 97-98. (in Russian)Google Scholar
- 243.Gai S. MOZART: A Concurrent Multilevel Simulator // IEEE Transaction on Computer-Aided Design. -1988. -Vol. 7, No. 9. -P. 1005-1016.Google Scholar
- 244.Saleh R., Antao B., Singh J. Multilevel and Mixed-Domain Simulation of Analog Circuits and Systems // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. -1996. -Vol. 15, No. 1. -P. 68-81.Google Scholar
- 245.Saleh R., Jou S.J. Mixed Mode Simulation and Analog Multilevel Simulation. -Kluwer Academic Publishers, 1994. -320p.Google Scholar
- 246.Chadha R., Visweswariah C., Chen C.F. Multilevel Mixed-mode A/D Simulator // IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. -1992. -Vol. 11, No. 5. -P. 575-586.Google Scholar
- 247.Mayaram K., Chern J.H., Yang P. Algorithms for Transient Three-Dimensional Mixed-Level and Device Simulation // IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. -1993. -Vol. 12, No. 11. -P. 1714-1726.Google Scholar
- 248.Cloutier J., Bourgault M., Fauvel S., Roy C., Cerney E. and Gecsei J. An Object-Oriented Mixed-Mode Hierarchical VLSI Simulator // Proceedings of Canadian Conference on VLSI CCVLSI’86. -Montreal, 1986. -P. 203-208.Google Scholar
- 249.Saleh R., Yang A. Modeling Mixed Systems with Spice 3 // IEEE Circuits & Devices. -1993. -Vol. 1. -P. 7-10.Google Scholar
- 250.Gorshkov K. The simulation technique for large-scale tree structured interconnects // IEEE Industrial Engineering, Applications and Manufacturing (ICIEAM). -Chelyabinsk, Russia, 2016. -P. 1-6.Google Scholar
- 251.Melikyan V.Sh. Optimization of timing parameters of digital circuits elements // Elektronika i svyaz, Vol. 4, No 2, Kiev, 1998. -P. 249-253. (in Russian)Google Scholar
- 252.Melikyan V.Sh., Nazinyan S.M. Power consumption algorithm of digital ICs//Simulation, optimization, control, SEUA, Yerevan, RA, Vol. 4, Yerevan, 2001. -P. 159-166. (in Armenian)Google Scholar
- 253.Liu C., Li Y., Du Y., Du L., Wang T. Hybrid thermal aware reconfigurable 3D IC with dynamic power gating architecture // IEEE Semiconductor Technology International Conference (CSTIC). -Shanghai, China, 2017. P. 1-3.Google Scholar
- 254.Jing T., Hong X. A Novel And Efficient Timing-Driven Global Router For Standard Cell Layout Design Based On Critical Network Concept//IEEE International Symposium on Circuits and Systems (ISCAS). -Scottsdale, Arizona, USA, 2002. -P. I165-I168.Google Scholar
- 255.Liao I.M.J., Su C.F., Chang A.C.Y., Wu A.C.H. A Carry-Select-Adder Optimization Technique for High-Performance Booth-Encoded Wallace-Tree Multipliers // IEEE International Symposium on Circuits and Systems (ISCAS). -Scottsdale, Arizona, 2002. -P. I257-I259.Google Scholar
- 256.Li Z., Wu W., Hong X. Incremental Placement Algorithm for Wirelength and Congestion Optimization//Chinese Journal of CAD/CG. -2003. -Vol. 15, No. 6. -P. 651-655.Google Scholar
- 257.Yunfeng W., Jinian B., Qiang W., Heng H. Re-synthesis after Floor-planning for Timing Optimization // IEEE International conference on ASIC (ASICON). -Beijing, China, -2003. -Vol. 1. -P. 212-215.Google Scholar
- 258.Ekpanyapong M., Balakrishnan K., Nanda V., Lim S.K. Simultaneous Delay and Power Optimization for Multi-level Partitioning and Floorplanning with Retiming // IEEE International Conference on Circuits and Systems. -2004. -P. 756-760.Google Scholar
- 259.Chang S.C., Marek-Sadowska M., Cheng K.T. Perturb and Simplify: Multi-level Boolean Network Optimizer // IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. -1996. -Vol. 15, No. 12. -P. 1494-1504.Google Scholar
- 260.Kannan L.N., Suaris P.R., Fang H.G. A methodology and algorithms for post-placement delay optimization//ACM/IEEE 31st Design Automation Conference. -San Francisco, 1994. -P. 327-332.Google Scholar
- 261.Huisman L.M. Correlations between Path Delays and the Accuracy of Performance Prediction // IEEE International Test Conference. -Washington, 1998. -P. 801-808.Google Scholar
- 262.McGeer P.C., Saldanha A., Brayton R.K., Sangiovanni-Vincentelli A.L. Delay Models and Exact Timing Analysis. Logic Synthesis and Optimization. -Kluwer Academic Publishers, 1993. -196p.Google Scholar
- 263.Lavagno L., Keutzer K., Sangiovanni-Vincentelli A.L. Synthesis of Hazard-Free Asynchronous Circuits with Bounded Wire Delays // IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. -1995. -Vol. 14, No. 1. -P. 61-86.Google Scholar
- 264.Saldanha A., Brayton R.K., Sangiovanni-Vincentelli A.L. Circuit Structure Relations to Redundancy and Delay // IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. -1994. -Vol. 13, No. 7. -P. 875-883.Google Scholar
- 265.Jiang Y.M., Krstic A., Cheng K.T., Marek-Sadowska M. Post-Layout Logic Restructuring for Performance Optimization // ACM/IEEE 34th Design Automation Conference. -Anaheim, California, 1997. -Vol. 11, No. 4. -P. 241-246.Google Scholar
- 266.Parodi C.G., Agrawal V.D., Bushnell M.L., Wu S. A Non-Enumerative Path Delay Fault Simulator for Sequential Circuits // IEEE International Test conference. -Atlantic, 1999. -Vol. 15, No. 5. -P. 107-110.Google Scholar
- 267.Gremoux S., Azemard N., Auvergne D. Algotithms for Path selection: a comparative study. -Kluwer Academic Publisher, 1997. -356p.Google Scholar
- 268.Hsino M.S. Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits // IEEE Conference Design Automation and Test in Europe (DATE). -Munich, 1999. -P. 175-179.Google Scholar
- 269.Balkir S., Dundar G., Ogrenci A.S. Analog VLSI Design Automation. -CRC Press, 2003. -275p.Google Scholar
- 270.Kankkunen A., Andersson M., Valtonen M. MOSFET Level 3 Model in APLAC. Report CT‑9. -Finland, 1991. -23p.Google Scholar
- 271.Bagdasarian H., Melikyan V., Nshanian M., Uzunoglu N. Computer modeling of fiber-optic communication systems // Trans black sea region symposium on applied electromagnetism. -Athens, 1996. -P.OPSY 9.Google Scholar
- 272.Gala K., Zolotov V., Panda R. On-chip inductance modeling and analysis // ACM/IEEE 37th Design Automation Conference. -Los Angeles, 2000. -P. 63-68.Google Scholar
- 273.Tsividis Y. Operation and Modeling of the MOS Transistor. -New York: McGraw-Hill, 1999. -356p.Google Scholar
- 274.Ciletti M.D. Advanced Digital Design with the Verilog HDL.-Prentice Hall, 2003. -982p.Google Scholar
- 201.Melikyan V., Shahinyan T., Melikyan H. A digital cell macromodel considering radiation affect//Manual of Engineering Academy of Armenia. Vol. 1. No. 3, Yerevan, 2004.-P. 585-588. (in Armenian)Google Scholar
- 275.Kleitz W. Digital Electronic with VHDL.-Prentice Hall, 2004. -960p.Google Scholar
- 276.Melikyan V. The Simulation of Digital Circuits Taking into Account the Destabilizing Factors // Fourth national conference on Semiconductor Microelectronics. -Tsakhkadzor, 2003. -P. 240-243.Google Scholar
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