Packaging of Power Devices

11.1 The Challenge of Packaging Technology

The operation of a power semiconductor device produces dissipation losses. The order of magnitude of these losses shall be estimated in the following example:

IGBT module BSM50GB120DLC (Infineon) mounted on an air-cooled heat sink

Operation conditions: I _C  = 50 A, V _bat  = 600 V, R _G  = 15 Ω, T _j  = 125 °C,

f = 5 kHz, duty cycle d = t _on /(t _on  + t _off ) = 0.5

The following parameters can be extracted from the data sheet:

Forward voltage drop: V _C  = 2.4 V

Turn-on energy loss per pulse: E _on = 6.4 mW s

Turn-off energy loss per pulse: E _off = 6.2 mW s

For details on E_on see Figs. 5.20 and 5.21. A simplified calculation can be done with Eq. (10.4), a more exact determination is done with the oscilloscope, see Eq. (9.33). For details on E _off see Fig. 10.6, for simplified calculation Eq. (10.6) is useful.

Losses created by the leakage current can usually be neglected in modern IGBT and MOSFET applications. Therefore total power dissipated in the device is the sum of on-state and switching losses :

$$ P_{V} = P_{cond} + P_{on} + P_{off} = d \cdot I_{F} \cdot V_{C} \,+ \,f \cdot E_{on} \,+ \,f \cdot E_{off} $$

(11.1)

This amounts to 123 W for the given example. These losses are marginal compared to the controlled power of approximately 30 kW. To calculate the efficiency an additional free-wheeling diode has to be taken into account; for most applications a half-bridge configuration of two switches in series must be considered. Nevertheless, the efficiency of the power control circuit is in the range of 98%.

However, 123 W of power losses have to be extracted from an IGBT switch with an area of about 1 cm² which requires a heat flux density of 123 W/cm² or 1.23 MW/m². The heat flux density can even amount to the 2–3 fold value for an assembly on a water-cooled heat sink and with maximum utilization of the module capability. Figure 11.1 relates this power loss to that of other heat sources.

Fig. 11.1

Heat flux density of different heat sources, inspired by Dr. W. Tursky, Semikron

The heat flux density of a power semiconductor chip exceeds that of a stovetop of a conventional kitchen stove by more than one order of magnitude and outranges a Pentium 4 microprocessor. Therefore, a power module has to provide a high thermal conductivity. Additionally, a power device package has to meet a number of requirements:

• High reliability, i.e. a long lifetime in application and therefore a high durability under alternating load conditions (power cycling stability)

• High electrical conductivity of the components to achieve low undesirable (parasitic) electrical properties (parasitic resistance, capacity and inductivity)

• For power modules additional electrical insulation between switches and between circuit and heat sink.

The solution to this problem is by no means trivial and it is today one of the most exciting challenges for engineers. Power modules are the prevalent types of packages in power electronic applications and they will be discussed in detail in the following chapters.

11.2 Package Types

A substantial criterion for the selection of an appropriate package type is the power range of the semiconductor device. A survey of power ranges is given in Fig. 11.2.

Fig. 11.2

Power range of modern semiconductor devices (2017) together with the predominant package type

Discrete packages are prevailing in the range of small power. These packages are soldered to a laminated ‘printed circuit board’ (PCB ) for application. Since the generated power losses are relatively small, the requirements for heat dissipation are unincisive. These packages are mostly designed without internal insulation with the consequence, that only a single switch can be integrated in one package. The most common package of this type is the ‘transistor outline’ (TO) package .

The discrete design has to fulfill the following functions:

• Conduction of load current and control signals

• Dissipation of heat

• Protection against environmental influences

Capsule s also belong to the discrete packages. They are applied for the high power end of the range that is not yet reached by power modules. Capsules are not equipped with an internal insulation. They can be cooled from two sides. A power chip can have the size of a whole wafer in the peak performance range. Therefore, the circular footprint of the capsule is the ideal package for circular chips. Because of its shape, this package is also known as “hockey puk”.

A thyristor from Mitsubishi for 1.5 kA with 12 kV blocking voltage is packaged in a capsule. Thyristors in capsules from Infineon are specified for 3 kA with 8.2 kV, and recently developed thyristors for HVDC -applications are rated for 5.6 kA with 8 kV blocking voltage. The ‘chip’ in these packages consists of a complete 6 inch wafer with a diameter of approximately 150 mm.

Mitsubishi offers a gate turn-off thyristor (GTO) in a capsule with a chip fabricated from a single 6 inch wafer (150 mm) which is specified for 6 kA with 6 kV blocking voltage.

In contrast to discrete packages power semiconductor modules are characterized by:

• an insulated architecture in which the components of the electrical circuit are dielectrically insulated from the heat dissipating mounting surface,

• several single functions (phase leg circuit), often with paralleling of chips

Power semiconductor modules are dominating in the range of more than 10 A for blocking voltages of 1200 V and above. They are characterized by the integration of multiple functions (for example converter-inverter-brake topologies, CIB) in the lower power range. In the high power area, Infineon offers a module with 6.5 kV IGBTs and the associated freewheeling diodes with a continuous maximum current of 900 A. For 1200 V blocking voltage, Infineon produces a module specified for 3.6 kA continuous current which contains 24 IGBT chips in parallel and 12 freewheeling diodes in parallel. These examples show that modules have penetrated deep into the high power range which was formerly dominated by capsules. This trend will continue.

11.2.1 Capsules

Figure 11.3 displays the internal construction of a capsule in a simplified schematic view. The silicon device (e.g. a thyristor) is mounted between two metal discs in order to homogenize the pressure and to avoid pressure peaks. Molybdenum is the ideal material for this purpose because of its great hardness and its well adapted coefficient of thermal expansion. In the architecture shown in Fig. 11.3 the silicon device is rigidly coupled to one of the molybdenum discs on the anode side and pressed to the second molybdenum disc on the cathode side. Alignment features to center the chip inside the package are not shown in Fig. 11.3 for clarity, neither is the gate contact spring displayed, which is guided by a slot in the cathode compression piece to the center of the silicon device. The package is hermetically sealed by welding together the two metal latch rings.

Fig. 11.3

Internal construction of a capsule (simplified)

A complete electrical and the thermal contact will only be established by the application of a defined pressure to the package, which is typically in the range of 10–20 N/mm².

The interconnection between the silicon device and the molybdenum discs can vary for different package sizes and manufacturers. For small chip diameters up to 5 cm, solder interfaces are feasible. But care must be taken to select a solder material, which will show only little plastic creep under high pressure. For larger diameters of the device alloyed interfaces are generally preferred. Also designs without any rigid connection between Mo and Si are available, which allow a floating of the power device. A progressive technology for the interconnection of silicon and molybdenum is a diffusion sinter technique: The partners to be connected are equipped with a noble metal plating, a silver powder is applied to the connecting surfaces and a very reliable connection is established by sintering the interface layer at a high pressure and temperatures of approximately 250 °C [Kuh91].

Mostly conventional devices are packaged in capsules: Diodes, thyristor s, GTO s and the GCT s derived from the GTO. The advantages of capsules are:

• Compact design with good relation between device surface area and package surface area

• Cooling of both device surfaces

• No wire bonds – wire bonds generally represent a reliability constrictive feature

• Few or no rigid interconnections between materials with different coefficients of thermal expansion

A high reliability can be expected from the last two factors. The disadvantages of capsules are:

• No dielectric insulation – the user has to provide for insulation in the application

• Higher effort in the mounting assembly – a defined uniaxial high pressure must be established and maintained

Due to its advantages the capsule package was also adapted as a package for IGBTs. But IGBTs are today produced only in a small chip size compared to thyristors. The reason is the high cell density of modern IGBT chips which would result in a yield problem caused by single cell defects with increasing chip size. The largest commercially available IGBT has an area of 300 mm². Furthermore, the simplicity of paralleling fast switching IGBTs compared to the difficulty of paralleling slow switching thyristors, together with the thermal disadvantage of large area chips, does not produce a market pressure to develop larger area IGBTs. However, for the adaptation of the capsule package for IGBTs, the parallel arrangement of quadratic chips in a so called ‘presspack IGBT ’ is a technological challenge.

An example for a presspack IGBT is illustrated in Fig. 11.4. The chips are assembled on a large molybdenum disc, each chip equipped with a collector side small Mo square. Alignment frames are positioning the chips relative to each other. Small Mo squares with cut-outs for the gate contact area are placed on the emitter contacts. The gate connection is implemented by springs, which are guided by another alignment structure. The upper pressure element has to transmit a uniform pressure to each of the chips below. To press each of the 21 paralleled IGBTs with an identical pressure requires maintaining very tight tolerances for every part of the package. For understanding of the system, electrical as well as thermal contact resistances have to be considered [Pol13a].

Fig. 11.4

Presspack IGBT: emitter pressure element (left), arrangement of the chips (right)

Integrated in the upper pressure element, a printed circuit board – carrying the gate resistors in ‘surface mounted device’ (SMD) technology – is installed. The complex construction of a presspack IGBT results in a considerable increased demand on the precise alignment of a multitude of parts and on the allowable part tolerances compared to a semiconductor module . Higher reliability in active power cycling compared to modules was expected, however not achieved in experimental tests [Tin15]. At high power load a deformation of the presspack resulting from internal temperature gradients occurred. It leads to inhomogeneous pressure distribution and even partially opening of contacts at outer positions [Pol13b]. The found failure modes were gate oxide damage and micro arcing [Tin15].

11.2.2 The TO-Family and Its Relatives

Discrete packages are also very common in the lower power range. Today, this field is dominated by the ‘transistor outline’ (TO) family. The principle design is shown in Fig. 11.5.

Fig. 11.5

TO package, principal design

The TO package family comprises an extensive set of standardized package outlines, the most popular representatives are the TO-220 and the TO-247 package. In these standard packages, the power silicon chip is soldered directly to a solid copper base, which serves as mounting surface. Therefore, the package has no inherent electrical insulation. The contact leads or contacts legs are fixed by a ‘transfer mold ’ housing. One of the leads is directly connected to the copper base, the others are connected to the load and control contact areas on the silicon chip by aluminum wire bond s (Fig. 11.5).

The difference in thermal expansion between the silicon chip and the copper base limits the reliability of this package. An improvement in this respect is the ISOPLUS package introduced by IXYS. As illustrated in Fig. 11.6, a ceramic substrate replaces the solid copper base, thus adapting a technology which is successfully applied in power modules. This design exhibits a number of advantages compared to the standard TO package:

Fig. 11.6

ISOPLUS package with TO outline, but with insulated base

• better adaptation of thermal expansion resulting in higher reliability

• internal insulation

• smaller parasitic capacity compared to a standard TO package mounted on a heat sink with an external insulation polyimide foil (for details refer to Sect. 11.5)

At the first glance, the smaller thermal conductivity of the ceramic layer with respect to copper appears as a serious drawback. However in a system, where several discrete packages – which typically show different potentials at their copper base – are mounted on a single heat sink, the ceramic insulation system generally is superior to the insulation of standard TOs by externally applied electrically insulating foils.

The prevalent power device packaged in a TO housing is the MOSFET . For this device, a drastic reduction of the electrical on-state resistance R _on has been accomplished in the last years. As a consequence, a fundamental weakness of this package design is emerging: The TO package has a parasitic electrical resistance in the same order of magnitude as the on-state resistance of a modern MOSFET device!

The contact leads are a major limiting factor. Their electrical resistance can be calculated by

$$ R_{Z} = \rho \cdot \frac{l}{A} $$

(11.2)

Considering a copper input lead and a copper output lead with a cross section of 0.5 mm² and a length of 5 mm each, the specific electrical resistance of copper ρ _Cu  = 1.69 µΩ cm yields a total resistance of 0.34 mΩ. For a mean current of 50 A, the power loss

$$ P_{Z} = R_{Z} \cdot I^{2} $$

(11.3)

dissipated in these leads amounts to approximately 0.85 W. Since the contact leads are cooled only marginally, they are heated up by the ohmic losses to temperatures, which can get close to the melting temperature of the solder alloy applied for the PCB solder contact [Saw00]. This effect damages the solder contacts and reduces the reliability.

Since the through holes for PCB mounting are standardized and since insulation requirements demand to maintain minimal clearance distances between the leads, the lead cross section cannot by increased by simply implementing wider leads (Fig. 11.7). But it was possible to increase the cross section by improving the shape of the leads as shown in the right schematics in Fig. 11.7 and thus enhance the current capability of the TO package by 16%. This upgraded version of a TO-247 package is labeled as ‘super-247’ package by the manufacturer.

Fig. 11.7

Reduction of the electrical resistance of contact leads in a TO package [Saw00]

The evolution of PCB technology established the ‘surface mounted device’ (SMD) technology for component packages. This technology allows to assemble components on both sides of the PCB and facilitates multilayer PCBs with buried inner layers. Since the through hole mounting technique of classical TO packages is not compatible with this assembly process, a new generation of packages was developed as shown in Fig. 11.8. The standardized package outlines were equipped with contact leads for SMD mounting. For the ‘super’ version of this package, not only the contact leads are designed as short as possible – allowing more area for larger silicone devices – but also the wire bond connections were optimized. These improvements result in a reduction of the parasitic inductance of the package of 33% according to [Saw00].

Fig. 11.8

For SMD technology optimized package design [Saw00]

A general weakness of TO packages and their SMD counterparts is the use of aluminum wire bonds, which contribute to the parasitic ohmic resistance of the package. Improvements are attempted by the implementation of thicker wires and/or by an increase of the number of wire bonds. Additionally, the parasitic inductance of the bond wires and the limited heat transport capability supported the search for better alternatives, e.g. by replacing the emitter bonds by copper metal sheets.

A revolutionary solution was introduced by the US American company International Rectifier, which completely eliminates the problematic contact leads, as well the bond wires. This ‘DirectFET ’ package is displayed in Fig. 11.9. The same package is offered as “CanPack” from Infineon. The emitter and gate contacts of the silicon device are equipped with a solderable surface metallization. A so called ‘drain clip’ is attached to the drain contact of the device by a solder connection. This package is mounted on the PCB surface in a ‘flip chip’ fashion, were the SMD compatible solder connections for the gate, emitter und drain are established in a single reflow solder step.

Fig. 11.9

DirectFET package [Saw01]

Beside the low effort mounting procedure, the advantages of this package concept stem from the facts, that virtually no limitation of the current capability originates from contact leads and that parasitic inductance generated by bond wires is completely eliminated. Furthermore, a double-sided cooling of the package is possible, whereas the drain clip can dissipate significantly more heat than can be extracted through the PCB.

Nevertheless, no complete encapsulation is provided by this package, which leaves the sensitive silicon device unprotected against humidity and corrosive atmosphere influence. Nevertheless, a high humidity reverse bias test (see Chap. 12) showed positive results [Hof13]. Furthermore, the visual access to the solder interconnection beneath the package is nearly impossible, which impedes the quality control of the assembled PCB. The application and field experience with this new package design will show, if this concept will prevail.

However, the combination of the ‘lead frame ’ construction with the ‘transfer mold’ technology, as was developed and optimized with the discrete TO packages, has lead to a powerful group of descendants: the transfer mold ‘intelligent power module ’ (IPM) packages. In these packages, the advantages of both technologies were merged with the integration of various functions in a single package. Figure 11.10 shows an example of an IPM transfer mold package , containing a three phase inverter together with their driver ICs.

Fig. 11.10

Transfer mold DIP-IPM package from Mitsubishi

The internal structure of such a transfer mold IPM device as shown in Fig. 11.11 allows to comprehend the high potential of this packaging concept, which today is dominating the field of low power IPMs worldwide. Despite of all the limitations of this package design discussed before, the manufacturing process of these lead frame packages is highly optimized and very competitive. In production, the lead frames are connected to each other by the frame elements, forming a continuous band of such lead frames, ideal for automated assembly. After the chip soldering and wire bonding, the band is separated into single lead frames and subjected to a transfer mold process, which completely encapsulates the internal structure. Now the leads are fixed by the plastic encapsulation and the remaining supporting lead connections, which connect the ductile contact leads during the assembly, are stamped out.

Fig. 11.11

Internal structure of the DIP-IPM package from Mitsubishi

Nowadays, more than 10 million of these transfer mold type IPM packages are produced every month, dominating the field of low power applications in the power semiconductor market.

11.2.3 Modules

As a result of the isolated construction, power modules provided substantial advantages in application. Soon after the first insulated power module was introduced by Semikron in 1975, this new architecture penetrated the market, even though the first design was rather complicated with a multitude of interfaces. Figure 11.12 shows the successor of this first power module, which today is still manufactured in large quantities. Shown here is the fifth generation design with an identical package outline as the first power module, but with an upgraded inner construction.

Fig. 11.12

Architecture of a classical thyristor power module: exterior view (a), inner construction (b) and cross section schematics showing the layer sequence (c)

The thyristor chip, which is equipped with solderable metallization on the anode, cathode and gate contact areas, is connected to the contact leads by solder interfaces. The cathode connector consists of a composite material with a coefficient of thermal expansion adapted to that of silicon. The anode contact of the silicon chip is joined to a molybdenum plate. This intermediate layer is required to accommodate the difference in thermal expansion between silicon and copper. The molybdenum plate is then soldered to a compact copper terminal, which conducts the current to the anode. The copper terminal is again soldered to the copper surface of a ceramic ‘direct bonded copper’ (DBC) substrate, than provides the electrical insulation. The substrate is attached to the base plate by another solder layer. In sum, the construction contains five solder layers. Despite of the complexity of this construction, this power module is manufactured these days in a high production quantity on an automated assembly line.

The cross section image in Fig. 11.12 visualizes the numerous interfaces that the heat flow has to overcome on his passage from the silicon device to the base plate and further into the heat sink, which is not shown in the schematics. Since every solder layer has a small risk of the formation of solder voids, the multitude of solder interfaces represent an increased risk factor for potential sources of error.

The introduction of advanced power devices like IGBT s or MOSFETs has induced the development of a package concept capable of housing multiple chips per electrical function in parallel. This architecture has emerged to the ‘standard’ or ‘classical’ module design in power electronics. The example displayed in Fig. 11.13 illustrates the general features of this concept: The top side contact of the silicon device is connected via aluminum wire bonds. The molybdenum adaptation plate and the bottom side copper terminal are completely eliminated. Trenches to form current tracks comparable to the familiar PCB in low power electronics structure the upper copper layer of the DBC substrate . Several power chips are directly soldered to these copper tracks and connected to other tracks by aluminum wire bonds. Powerful load current terminals are soldered to the load current tracks of the substrate.

Fig. 11.13

Classical base plate module in schematic cross section (top) and as halfbridge IGBT module with two chips per switch (bottom)

Table 11.1 lists the layer thicknesses typically implemented in standard module s displayed in Fig. 11.13. This generic construction is found in 70–80% of all power modules produced by European manufacturers (Infineon, Semikron, IXYS, Danfoss, Dynex) and is also common in modules produce by Asian manufacturers.

Table 11.1 Layer thickness in module designs with base plate

The thickness of the ceramic layer is 0.63 mm in older generation modules, newer generation modules with base plate have a ceramic thickness of only 0.38 mm for improvement of thermal resistance. The thickness of ceramic plates is specified in the unit mil (1 mil = 1 × 10⁻³ inch = 25.4 µm), so that 0.635 mm is equivalent to 25 mil and 0.381 mm is equal to 15 mil. The substrate is attached to the base plate by a solder interface. Differences in solder thickness between 0.07 and 0.1 mm have a marginal impact on the thermal resistance.

For modules requiring a higher thermal conductivity or higher insulation strength, Al₂O₃ ceramics are replaced by AlN ceramics. The standard thickness of AlN is 0.63 mm, but for assemblies with extreme requirements with respect to insulation strength, ceramics with a thickness of 1 mm are applied. The fabrication of AlN substrates requires an additional process step compared to Al₂O₃ substrates, since no oxides are available at the surface to form an oxide-oxide interface as in the DBC production. Therefore, an oxide layer has to be generated first or other bonding techniques have to be applied. This increases the costs for AlN substrates. Furthermore, the coefficient of thermal expansion of AlN (and thus also the CTE of an AlN-DBC) is smaller than that of Al₂O₃. This amplifies the difference in thermal expansion between the substrate and a copper base plate and reduces the lifetime of this interface under thermal stress. A countermeasure is to increase the thickness of the solder interface to 200 µm or more to reduce the strain in the interface [Yam03]. Spacers implemented before the solder process assure a homogeneous solder thickness. Another option applied in some high performance power modules is to replace the copper base plate by AlSiC , a metal matrix composite material. An AlSiC plate is manufactured by first forming a matrix of SiC with a controlled porosity and secondly filling the pores with liquid aluminum. The material parameters are determined by the ratio of both components and can therefore be tailored to the application.

While the implementation of AlSiC as material for the base plate has the advantage of an adaptable thermal expansion, it has the disadvantage of a reduced thermal conductivity compared to copper. This was the major reason that a module design concept without a base plate emerged. Even for copper as base plate material the base plate adds to the total thermal resistance in the vertical direction between the chip and the heat sink, so that systems without base plate should be advantageous. Figure 11.14 shows a schematic cross section of this architecture.

Fig. 11.14

Schematic cross section of a module without base plate

The applied substrates and solder materials are essentially the same as in modules with base plate. A value of 0.38 mm is the standard ceramic thickness for Al₂O₃ substrates, but thicknesses of 0.5 mm or 0.63 mm are also encountered. Especially for substrates with increased copper thickness for high current applications, thicker ceramics are preferred to enhance the mechanical robustness of the substrate (e.g. 0.4 mm Cu on both sides of a 0.5 mm Al₂O₃ ceramics). For AlN substrates 0.63 mm is the standard ceramics thickness. Other ceramic materials can easily be substituted in a module without base plate.

Modules without base plate are provided for example in the SKiiP -, MiniSKiiP- and Semitop module families from Semikron and in the EasyPIM series from Infineon. The packaging concept was available in several modules provided by IXYS for a long time. It is also applied in the insulated version of the TO-247 package. Since the solder interface between a base plate and the substrate is eliminated, only one single solder interface between the chip and the heat sink remains in this package type.

In contrast to base plate modules, no limitation of the substrate size must be obeyed in non base plate constructions. Therefore, complex circuits can be realized on a single substrate. The example of a substrate from a highly integrated module without base plate is shown in Fig. 11.15. It contains a single phase input rectifier and a three phase output inverter for a medium power frequency converter. Shunt resistors and a temperature sensor are also integrated.

Fig. 11.15

Internal structure of a modern power module with input rectifier, output inverter and sensors (left) and housing with spring contacts (right) (MiniSKiiP by Semikron)

The load, control and sensor terminals in this package concept are accomplished by identical springs. With this spring contact technology, a multitude of load and control contacts can be positioned at almost any location on the substrate, thus allowing a very flexible contact technology to realize a multitude of different circuits on the same package platform. Each spring can continuously conduct 20 A, higher currents can be attained by paralleling of springs.

Modules without base plate are not limited in footprint size. They require minimum effort in production and also minimize the number interconnections in complex circuits, thus reducing the number of potential sources of failure. On the other hand, sophisticated pressure systems have to be integrated into modules with large footprints to ensure an optimum thermal contact between the substrate and the heat sink. The impact of the capability of this pressure system on the thermal interface between the module case and the heat sink results in different thicknesses of the thermal interface layer in Table 11.2. Finally, modules without base plate not only have advantages like the improved thermal gradients inside the module, which reduce the thermal stress and therefore increase the reliability under active thermal cycling [Scn99]. The absence of a base plate also has some drawbacks. First, the thermal spreading of the base plate no longer helps to reduce the temperature distribution across the chip. Therefore, smaller chip sizes are preferred in non base plate designs. The second drawback is the missing heat capacity of the base plate, which increases the thermal impedance of the module in a range between 50 and 500 ms for isolated overload events in this time range.

Table 11.2 Layer thickness in module designs without base plate

A common problem for all module designs is the interface between the module case and the heat sink surface. Due to the geometric tolerances of the contact surfaces and the modification of bow by the bi-metal effect caused by thermal expansion, no perfect metal-to-metal contact can be achieved. The gaps have to be filled with a ‘thermal interface material ’ (TIM), which typically has a specific thermal conductivity in the range of 1 Wm⁻¹ K⁻¹. Even though this conductivity is a factor 30 better than air, the conductivity is more than a factor of 100 worse than that of most metal layers. Therefore, the thickness of the thermal grease has to be kept as small as possible without the risk of air gaps.

The application of the optimum thermal grease thickness during the mounting process on a heat sink is a serious quality issue for many users of power modules. Semikron therefore delivers the SKiiP module family already mounted on the customer heat sink with a controlled thickness of thermal grease. For modules with base plate, the thermal resistance of the interface between module case and heat sink is specified by a typical value in the data sheet R _thch , which amounts to roughly 50% of the internal thermal resistance from chip to case. While this interface is difficult to establish in a controlled process, it is of greatest importance for the thermal characteristic of the power module in application. Recently, several manufacturers of power modules offer pre-applied TIM layers on the interface to the heat sink with optimized lateral distribution to simplify the mounting process for customers.

11.3 Physical Properties of Materials

The properties of the materials used in a package design are fundamental for the characteristics of the module. The most important parameters are the thermal conductivity and the coefficient of thermal expansion (CTE) of a material, but the electrical conductivity and the heat capacity are also of great interest. It is therefore inevitable to know and consider the properties of the materials prior to their implementation into a power module package.

A survey of the thermal conductivity of the most important materials in power electronic packaging is shown in Fig. 11.16. The best of the ceramic materials used for insulation feature thermal conductivities in the range of metals. Beryllium oxide , which exhibits the highest thermal conductivity, had been used in power module designs in the early days of module history. Nowadays, this material is implemented no more due to the toxicity of BeO dust and the resulting threats and limitations in handling and disposal of this material. Second in line of the ceramic insulators in this survey is AlN . But substrates with AlN are more expensive than standard Al₂O₃ substrates, so that this material is implemented only when high power density requirements or a demand for high basic insulation makes it inevitable. Organic insulators like epoxy or polyimide (Kapton ^®) only provide a comparable low specific thermal conductivity.

Fig. 11.16

Thermal conductivity at room temperature of different materials frequently used in packaging technologies

Inherent to the performance of a power module in application are varying load conditions, which generate temperature swings. Differences in the thermal expansion of different materials stress the package. To minimize the stress induced by the thermal expansion between different adjacent layers, their CTE should be comparable (or more precisely in the presence of thermal gradients inside a stack of layers: the difference of the product of layer temperature and the CTE in adjacent layers should be as small as possible).

Figure 11.17 illustrates the fact, that the CTE of Si and Cu are quite different. It is therefore very unfavorable to connect both materials directly, as is the case in standard TO packages (Fig. 11.5). Implementing a ceramic substrate between the Cu base plate and the Si chip – which is a general concept of power modules – considerably reduces the thermal mismatch between adjacent layers and thus increases the lifetime. The adoption of Al₃O₃ DBCs with 0.3 mm Cu layers leads to similar stress in the two interconnection layers between chip and substrate and between substrate and base plate [Scn99]. Replacing Al₂O₃ DBCs with AlN DBCs reduces the stress from thermal expansion between the chip and the substrate but increases the stress between the substrate and a copper base plate. Implementing AlSiC base plates reduces the stress in the interface to the substrate in high performance power modules. The ratio of the two components of this metal matrix compound allows to adjust the CTE of the material to an optimal value for AlN substrates. On the other hand, a considerably reduced thermal conductivity is the consequence as shown in Fig. 11.16. Al₂O₃ as the prevailing ceramic material for power (DBC ) substrates is from the thermal expansion point of view the best compromise to attach to silicon on one side and to copper on the other.

Fig. 11.17

Coefficient of thermal expansion (CTE) at 25 °C of materials frequently used in package technologies. (*) Depending on the composition of compound

The organic insulation materials epoxy and polyimide (Kapton^®) have a wide elastic deformation range, so that the coefficient of thermal expansion is not of interest and is therefore omitted in Fig. 11.17. Otherwise, these organic insulators are characterized by a much higher breakdown voltage (refer to appendix C, D) and thus can be implemented in very thin layers. Table 11.3 gives a compendium of standard material parameters and standard thicknesses, which are established in the packaging technology. The comparison shows, that a polyimide layer has a more than 10 times smaller thickness compared to ceramic insulators for an equivalent breakdown voltage.

Table 11.3 Standard layer thickness of insulators and emanating properties

Despite of the small layer thickness, substrates based on organic insulators exhibit a smaller thermal conductivity than ceramic substrates [Jor09]. Additionally, the small layer thickness provokes a high electrical capacity, which as parasitic capacity interacts detrimental with the power circuit.

The comparison of all properties of the insulation materials delivers that AlN is technically the best choice as insulating material for power semiconductor packages, if BeO is abandoned due to its toxic characteristics. AlN possesses the highest thermal conductivity and it is indispensable by virtue of its high breakdown voltage for modules with a blocking capability >3 kV. However, AlN exhibits due to its brittle structure an increased risk of fracture and thus inflicts a greater challenge for the industrial production of modules. The high bending strength of Si₃N₄ allows reducing the layer thickness to achieve a heat transfer coefficient comparable to AlN in the voltage range up to 1200 V. Si₃N₄ substrates are currently evaluated by several groups for automotive applications.

11.4 Thermal Simulation and Thermal Equivalent Circuits

11.4.1 Analogy Between Thermal and Electrical Parameters

The differential equations describing the physical process of one-dimensional heat conduction have the same form as the set of equations characterizing the one-dimensional electrical conduction. By exchanging the corresponding parameters, a thermal problem can therefore be transformed into an electrical problem and vice versa. Due to the equivalence of the differential equations, all operations performed for electrical networks can be transferred to thermal network s, especially the approximation of a continuous conduction line by a set of discrete elements in a lumped network. Since a variety of tools is available today for the simulation of electrical networks, thermal problems can be calculated by solving the equivalent electrical circuit.

The standard procedure is to first transform the thermal parameters into the corresponding or analogue electrical parameters. Then the corresponding equivalent network can be solved by applying advanced electrical network simulation tools. Finally, the results are transformed back into the thermal parameters. Table 11.4 gives a list of the fundamental corresponding parameters [Lap91].

Table 11.4 Equivalent electrical and thermal parameters

From these fundamental parameters, other corresponding parameters can be derived. The electrical time constant as the product of resistance and capacity for example has its correspondence in the thermal time constant, defined as the product of thermal resistance and thermal capacity.

While, at the first glance, the correspondence between electrical and thermal parameters seems to be perfectly symmetrical, there is a difference which destroys that perfect symmetry. This difference is the explicit appearance of the temperature in the thermal equations. To examine this difference closer, let us consider the definition of the thermal resistance R _th between the geometrical locations a and b:

$$ R_{th(a - b)} = \frac{{T_{a} - T_{b} }}{{P_{V} }} = \frac{{\Delta T}}{{P_{V} }} $$

(11.4)

In the electrical theory, Ohm’s law postulates that the ohmic resistance is constant and therefore independent of the voltage, if the boundary condition of a constant temperature is fulfilled. This boundary condition reflects the fact, that material properties are generally dependent on temperature. But since the temperature is an explicit parameter in the definition of the thermal resistance, a correspondence to Ohm’s law in the thermal theory with the boundary condition T = const. is not reasonable. This means, that the thermal resistance is always temperature dependent [Scn06].

The temperature dependence of the specific thermal conductivity of silicon, aluminum and copper illustrates Fig. 11.18 according to [EFU99]. Following [Poe04], the temperature characteristic of silicon can be approximated between −75 and +325 °C by the expression

Fig. 11.18

Temperature dependence of the thermal conductivity of Si, SiC, Al and Cu. Data according to [EFU99] and [Fel09], solid line for Si calculated by Eq. (11.5)

$$ \lambda_{Si} = 24 + 1.87 \times 10^{6} \cdot {\text{T}}^{ - 1.69} \,{\text{Wm}}^{ - 1} {\text{K}}^{ - 1} \quad \text{with} \,\text{T}\;\text{in} \,\text{Kelvin} $$

(11.5)

The thermal resistance (11.4) is constant only if λ is temperature independent. This applies in good approximation between −50 and +150 °C for Al and Cu and for most other materials. In power electronic systems, the thermal resistance of silicon amounts to only 2–5% of the total resistance, so that a negligence of its temperature dependence results in most cases only in a small error. To eliminate this fundamental problem, a temperature dependent resistance can be simulated by using a voltage dependent resistor in the equivalent network, which is possible in most electrical network simulation tools.

Another general problem in thermal simulation is the interpretation of temperatures. Conventional reference points are the ambient temperature T _a , the heat sink temperature T _s , sometimes the case temperature T _c and the so called ‘virtual’ junction temperature T _vj . Three-dimensional systems that are not in a state of thermal equilibrium exhibit pronounced gradients of temperature in every layer of the system. So a single temperature values T _c or T _s must be clearly defined in a real system, in which the base plate (as the module case) and the heat sink surface are characterized by temperature distributions.

Especially, this holds true for the junction temperature T _j . In the power device where the power is dissipated, the greatest gradients of temperature are present. Thus, it is expedient to postulate a virtual junction temperature T _vj as a characteristic temperature of the silicon device. This parameter is defined by the measured voltage drop over a pn-junction for a small sense current, as was already discussed in Sect. 3.2.

The forward voltage drop of a pn-junction at very small current depends strongly on temperature. It is always decreasing with temperature. To use this effect to determine the temperature, the sensing current must be small enough, that a temperature influence of the sense current can be neglected. Typically a current density of 100 mA/cm² or lower is selected. Figure 11.19 shows a measurement of the forward voltage drop at the pn-junction of a 50 A diode measured at 50 mA as function of temperature. After determination of this calibration function, the junction temperature of the device can be measured by applying a sense current of 50 mA and measuring the voltage drop at an instant where the device is supposed neither to a forward current nor to a blocking voltage. Figure 11.19 compares the measured calibration function with the calculation according Eqs. (3.52), (3.53) and (3.55), resolved for V. As ideality factor, n = 1.05 was used in Eq. (3.55) for this fast recovery diode.

Fig. 11.19

Calibration of the pn-junction of a 50 A 1200 V Si-diode for use of the pn-junction as temperature sensor. Forward voltage drop at the pn-junction of the 50 A diode measured at 50 mA. Calculation according Eqs. (3.53) and (3.55)

Together with the calibration of this voltage drop at different ambient temperatures, this method delivers a convenient technique to determine the virtual junction temperature of a device without intrusion into the package. This technique works well with diodes and IGBT s. The pn-junction between the gate and the cathode can be used for this method for thyristors. For the MOSFET , the inverse diode can be utilized for the measurement of the virtual junction temperature; in this case the sense current is applied in reverse direction.

As pointed out before, there is no constant temperature on the surface of a real power device in non-equilibrium condition. The edges of the silicon chip have a lower temperature than the center of the chip, because the heat flux can propagate not only vertically towards the heat sink, but it can also spread out away from the chip center, which can be envisaged by the cross-sectional illustrations in Figs. 11.13 and 11.14. This phenomenon is called heat spreading . The exemplary simulation in Fig. 11.20 illustrates the impact of a power dissipation of 200 W, homogeneously generated in the volume of a 12.5 × 12.5 mm² IGBT chip. The calculated temperature distribution reveals a center temperature, which is approximately 20 °C higher than the cooler edges of the chip.

Fig. 11.20

Simulated temperature distribution in a silicon chip with layers according to Fig. 11.14. Illustration from [Scn06]

An experimental validation of the simulated temperature distribution was presented in [Ham98]. The temperature was measured using a potential separated sensor, consisting of a phosphorescent powder at the end of a silica glass rod, which was excited by a laser. The temperature dependence of the phosphorescent radiation was used to measure the temperature at the tip of the silica glass rod. With this potential separated sensor, the surface temperature of an IGBT chip could be measured at different locations. The measured temperatures at the center and at the edge of the chip were related to the virtual junction temperature determined by the voltage drop for a sense current of 100 mA (Fig. 11.21). For a high load current, the temperature difference between center and edge was also found to be in the range of 20 °C. The results also show that the temperature T _vj is an average value for the real temperature distribution, which is shifted towards the hotter chip center temperature.

Fig. 11.21

Relation between the surface temperature of an IGBT and the virtual junction temperature T_vj, according to [Ham98]

The reason for this shift towards the hot chip center temperature is found in the temperature characteristic of the voltage drop across the backside pn-junction of the IGBT (refer to Fig. 10.10, junction J ₁) for small currents. Although the temperature coefficient of the forward voltage drop of an IGBT is positive in the range of nominal current, the voltage drop for small currents is only determined by the physical properties of the pn-junction and thus exhibits a negative temperature coefficient. This results in a smaller resistance of the hot chip areas and therefore implies a greater weight of the hot areas in the averaging process by the sense current flow. This is a desirable feature of the temperature measurement because the emphasis on the areas of higher temperature reduces the difference to the maximum temperature in the real chip. But it should be kept in mind, that the maximum temperature can still be considerably higher than the virtual junction temperature for large chips and high load currents.

Determining the junction temperature from the temperature dependence of electrical parameters of the chip itself has the great advantage that no sensors are necessary and thus no intrusion into a module package or modifications by the manufacturer are required. Any temperature sensitive electrical parameter (TSEP) of a device can in principle be applied for a sensorless measurement of the chip temperature [But14]. However, it should be emphasized that different temperature values will be delivered by different measurement methods. Especially for comparison between different measurements or to FEM simulation results, the geometrical interpretation of the measured temperature value is essential.

The most common TSEP method is the V _j (T) method, also named V _CE (T) method, as discussed above which delivers the virtual junction temperature T _vj . For fast switching devices like modern IGBTs the temperature can be measured 100 µs after turn-off of the load current. An extended investigation of the averaging effect of the sense current in [Scn09] shows that the measured temperature value corresponds to the area related average value of the temperature.

However, there are two major limitations of sensorless measurement methods. The first limitation is the fact, that most of these methods cannot directly be applied to determine the chip temperature in real switching applications like a PWM-operation in a frequency inverter. There is no simple possibility of applying defined operating conditions for TSEP evaluation in a real inverter operation.

The second limitation is attributed to the averaging process of these methods. For a single chip only one characteristic temperature value is delivered with no information on the temperature difference between the hot center and the cooler corners of the chip. This problem becomes even more pronounced in case of parallel chips. If one of the parallel chips has a higher thermal resistance – for example due to a deficient solder quality – its higher temperature will only have a small impact on the average value.

The measurement technique for determining the other reference point temperatures T _c and T _s is also not trivial. For the measurement of the case temperature T _c , which is a common reference point for classical modules with base plate, a drilling has to be incorporated into the heat sink exactly in the center of the silicon device generating the power losses as displayed in Fig. 11.22. This measurement therefore requires the knowledge of the exact position of the chips inside the module . This drilled hole interferes with the heat flux into the heat sink. However, due to the thermal spreading in the base plate of classical modules, this disturbance results only in a deviation of ≤5% form the undisturbed value, as was verified by thermal simulation.

Fig. 11.22

Definition of the case temperature T_c and the heat sink temperature T_s

The impact of such a drilled hole for temperature sensing on a module without base plate is much more severe because of the non-existing spreading of a base plate. It was proposed by [Hec01] to replace the through hole in the heat sink by a blind hole, which only reaches up to 2 mm underneath the heat sink surface. This measurement configuration has the advantage, that the thermal interface between module and heat sink is integrated in the heat path. This method can be applied for any type of module. The reference temperature defined by this geometry is called heat sink temperature T _s (in older publications often indicated by T _h ).

In contrast to the measurement of the virtual junction temperature, the measurement of the case or heat sink temperature is mostly restricted to equilibrium state conditions. The transient response of thermocouples is in the range of 100 ms and more, so they cannot be utilized for the measurement of fast temperature evolutions in power modules, which have a typical time constant for the internal thermal resistance of approximately 1 s.

These considerations shall illustrate that the thermal characterization of a power electronic system is never easy – neither by simulation nor by measurement. A lot of experience and a critical mindset are necessary to select the right model and to interpret simulation results. Temperature measurements have to be carefully reviewed as well. It is mandatory in scientific publications to discuss the applied methodology for temperature measurements for the interpretation of results. The thermal characterization is one of the most difficult tasks in power electronic systems and only succeeds by combining experimental skill with correctly applied thermal simulation.

11.4.2 One-Dimensional Equivalent Networks

In a one-dimensional equivalent network, the power dissipated in a thermal heat source is represented by a current source. A network of resistors and capacitors represent the thermal resistances R _th,i and the thermal capacities C _th,i of the analogue thermal system. The ground potential is equivalent to the ambient temperature. In the physically correct Cauer-model , the thermal capacities are connected from each node of the model to the ground potential. If power losses are generated in the system, the temperature will rise in the nodes and thermal energy is stored in the capacitors. The stored energy is proportional to the temperature difference to the situation before the power losses were applied; therefore, this network correctly describes the physical reality (Fig. 11.23).

Fig. 11.23

One-dimensional thermal equivalent networks

In contrast to the Cauer-model, the capacitors are connected in parallel to the resistors in the Foster-model. It should be noted that the values of the resistors and capacitors are different in both networks! The equivalent Foster-model has in total the same transient behavior as the Cauer-model with respect to the temperature of the first node next to the power source. While the internal nodes in a Cauer-model can be interpreted as geometrical locations in the system, this is not possible for internal nodes of the Foster-model. The feature, that pairs of Rs and Cs in a Foster-model can be exchanged without altering the transient response of the whole system might help to remember this important fact. The exchange of pairs of Rs and Cs in the Cauer-model will on the other hand alter the transient response of the system, as the exchange of layers in a real system would do. This missing link to the system geometry also implies that the values of the resistors and capacitors in the Foster-model cannot be calculated form material constants, as is the case for Cauer-models. Finally, a Foster-model cannot be divided, neither can two Foster-models be connected together, while both operations are possible for Cauer-models.

Those severe restrictions in the application of Foster-models lead to the question, why we use this type of model at all. The answer is, that the time dependent thermal resistance – often referred to as the ‘thermal impedance ’ Z _th of a system – can be expressed by a simple analytical expression. The model parameters $R_{i}^{{\prime }}$ and $C_{i}^{{\prime }}$ in this expression can be determined from the system response to a step function in power losses. By applying a least square fit algorithm, the parameters in the analytical expression can be optimized until the time response matches the transient system response, for example measured by a heating or cooling curve.

$$ Z_{th} = R_{th} (t) = \sum\limits_{i = 1}^{n} {R_{i}^{{\prime }} \cdot \left[ {1 - \exp \,\left( { - \frac{t}{{\tau_{i} }}} \right)} \right]} \,{\text{with}}\,\tau_{i} = R_{i}^{{\prime }} \cdot C_{i}^{{\prime }} $$

(11.6)

The values of the $R_{i}^{{\prime }} \,{\text{and}}\,\tau_{i}^{{\prime }}$ are often explicitly listed in data sheets of power packages. They allow a fast calculation of the transient response of a package to complex power distributions for application engineers.

The resistances and capacitors in the Cauer-model can be calculated straight forward from the material parameters and geometry:

$$ R_{th} = \frac{1}{\lambda } \cdot \frac{d}{A} $$

(11.7)

$$ C_{th} = c \cdot \rho \cdot d \cdot A $$

(11.8)

with layer thickness d, cross section area A, specific thermal conductivity lambda, specific heat capacity c, and specific density ρ. When the nodes of the equivalent network are chosen to be located in the center of gravity of each layer of homogeneous material, the thermal capacity of each layer is defined by the material parameter and the layer volume. The resistance between two nodes is then composed of two contributions, defined by the material constants and half the thickness of each of the layers in contact (Fig. 11.24). Power losses generated homogeneously in a layer are represented by current injected in the node of the layer and the voltages at the nodes represent the average layer temperature.

Fig. 11.24

Extraction of R_th and C_th values of a Cauer network from geometry and material constants of a layer system

With these extraction rules, a Cauer-model of a layer system can be derived, which allows a complete geometrical interpretation and all geometrical operations such as combining or dividing systems.

11.4.3 The Three-Dimensional Thermal Network

The one-dimensional Cauer-model is only a rough approximation for the complex geometry of layers in a real power module . The layers typically exhibit different cross sections and the resulting lateral heat spreading cannot be described by a one-dimensional model (refer Sect. 11.2, especially to the Figs. 11.13 and 11.14). The thermally high conductive copper layers extend the effective heat conduction area above the layers with a high thermal resistance (ceramic, thermal paste). These three-dimensional features can be accounted for by extending the Cauer-model to three dimensions as shown in Fig. 11.25. The nodes are arranged in a three-dimensional lattice; each node is connected to its neighbors via resistors.

Fig. 11.25

Three-dimensional model for a simple two-layer system showing the lattice of nodes with the interconnecting resistors, diagram from [Scn06]

The nodes in Fig. 11.25 are located in the center of each cuboid element. The resistors between the nodes are determined by the material parameters along the path, so that across the interface of two adjacent layers the resistors are determined by the material parameters of both layer materials.

Figure 11.25 also exemplifies that the number of elements is increasing fast in the three-dimensional model. Even though this simple system contains only 2 layers with 9 nodes for layer 1 and 25 nodes for layer 2, a total number of 86 resistors are necessary to connect the nodes. Additionally 34 capacitors have to be connected from every node to the ground potential if the transient response of the system is of interest. For a realistic model of a power semiconductor package, several hundred of nodes with more than a thousand elements are adequate. Such complex networks require fast network simulation tools and a suitable pre-processor to generate the input data from a given geometry. However, the simulation results reveal the temperature evolution in layers, which are not accessible to measurement without considerable interference with the system. Furthermore, the three-dimensional simulation is the only way to calculate the impact of disturbances by a measurement setup and allows quantifying the offset with respect to an undisturbed system. Finally, fast transient temperature evolutions in all layers other than the silicon device are virtually not accessible by measurement [Hec01] and only simulation models deliver the accurate data necessary for the thermal characterization of a power module package.

11.4.4 The Transient Thermal Resistance

A simulation of the transient thermal resistance or thermal impedance Z _th based on a three-dimensional model is shown in Fig. 11.26. Three different power module packages using AlN -substrates are calculated for comparison: two modules with base plate according to Fig. 11.13 with layer dimensions as listed in Table 11.1 and one module design without base plate according to Fig. 11.14 with layer thicknesses as given in Table 11.2.

Fig. 11.26

Transient thermal resistance simulated for different module designs based on AlN substrates. Figure from [Scn99]

The thermal impedance is small for a short single pulse below 50 ms and it is independent of the module design, because the heat is almost completely stored in silicon chip and the substrate. For large pulse length, the thermal impedance approaches the equilibrium value of the thermal impedance, which is the thermal resistance R _th . The comparison of the different designs reveals that the thermal resistance of the module without base plate is moderately smaller than the thermal resistance of the module with a Cu base plate. This is a consequence of the thermal resistance of the base plate in vertical direction. The thermal resistance of the module with AlSiC base plate is considerably higher due to the inferior thermal conductivity of AlSiC. This inferior thermal conductivity also increases the thermal impedance in the intermediate range between 50 and 500 ms compared to the copper base plate modules. However, the Z _th of the module without base plate features the highest values in this interval. This is a consequence of the missing thermal capacity of the base plate. Therefore, the module design without base plate possesses less buffer capacity for single pulse overload conditions between 50 and 500 ms.

However, the single pulse response of a system is relevant for a limited number of applications, only. A single pulse event draws maximum advantage out of additional thermal capacity in the system, because there is an infinite time to dissipate the heat after the end of the pulse. The situation is different in case of repetitive pulses. Then there is only limited advantage of the additional thermal capacity, in our case the base plate.

The temperature evolution in a system [described by Eq. (11.6)] for an infinite series of constant power pulses can be calculated analytically. For such a series of constant pulses of the constant power P _on during the time t _on followed by no power for the time t _off , we can calculate the stationary maximum temperature swing :

$$ \Delta T_{{{\text{max,}}\,{\text{stationary}}}} = P_{on} \sum\limits_{i = 1}^{n} {R_{i}^{{\prime }} } \frac{{1 - \exp \,\left( { - \frac{{t_{on} }}{{\tau_{i} }}} \right)}}{{1 - \exp \,\left( { - \frac{{(t_{on} + t_{off} )}}{{\tau_{i} }}} \right)}} $$

(11.9)

We can also calculate the minimum temperature of the stationary temperature ripple generated by a sequence of constant pulses:

$$ \Delta T_{{{\text{min,}}\,{\text{stationary}}}} = P_{on} \,\sum\limits_{i = 1}^{n} {R_{i}^{{\prime }} } \frac{{\exp \,\left( { - \frac{{t_{off} }}{{\tau_{i} }}} \right) - \exp \,\left( { - \frac{{(t_{on} + t_{off} )}}{{\tau_{i} }}} \right)}}{{1 - \exp \,\left( { - \frac{{(t_{on} + t_{off} )}}{{\tau_{i} }}} \right)}} $$

(11.10)

Both equations together deliver the stationary temperature ripple:

$$ \Delta T_{ripple,stationary} =\Delta T_{\hbox{max} ,\,stationary} { - \Delta }T_{\hbox{min} ,\,stationary} $$

(11.11)

If we define the duty cycle as the ratio d = t _on /(t _on  + t _off ), we can discuss the impact of the thermal capacity on the system response in more detail. For very low duty cycles, the single pulse characteristic as shown in Fig. 11.26 can be used as good approximation. In real applications, this applies to welding applications or some induction heating applications with long pauses between high current pulses. For motor drive applications, which are still the majority of all power electronic applications, the IGBTs as well as the diodes are under load during one half wave of the output current and under no load during the next half wave. It shall be simplified in a first approximation as a load duty cycle of 50%. Then the thermal impedance of the three systems of Fig. 11.26 compare as shown in Fig. 11.27. Here we see that the system without base plate is still inferior to the system with a copper base plate, but it is superior to the AlSiC base plate design in the whole frequency range. Due to the much smaller thermal conductivity of AlSiC, the heat stored in the base plate cannot be dissipated fast enough into the heat sink to give an advantage for the 50% duty cycle.

Fig. 11.27

Transient thermal resistance simulated for different module designs based on AlN substrates for a duty cycle of 50%

Equations (11.9) and (11.10) are also very useful to determine the ripple amplitude in equilibrium state. The difference between the maximum temperature and the minimum temperature defined by these equations delivers the amplitude of the temperature ripple in steady state condition. Figure 11.28 illustrates these dependencies.

Fig. 11.28

Temperature ripple for sequence of constant power pulses P_on

An application example shall be given. We consider a dissipated power of P _av  = 300 W in an application with an output power frequency of 5 Hz and a duty cycle of 50%. This is for example a slowly rotating electric motor fed by a variable speed drive with IGBTs. For the module with Cu base plate we get from Eq. (11.4) a temperature increase ΔT _jav  = 60 K using the thermal resistance of 0.2 K/W as follows from Figs. 11.26 and 11.27 for the stationary condition. During the pulse length of 100 ms we have to calculate

$$ \Delta T_{jmax} = \, Z_{thjc}^{ \cdot } P_{on} $$

(11.12)

with Z _thjc  = 0.13 K/W from Fig. 11.27 and P _on  = 600 W we get ΔT _jmax  = 78 K. The difference of ΔT _jmax and ΔT _av is ½ of the temperature ripple in the special case of 50% duty cycle, so that the temperature ripple amounts to 36 K. For the module without base plate we get, using 0.19 K/W, as result ΔT _jav  = 57 K; and with Z _thjc  = 0.135 K/W from Fig. 11.27 we get ΔT _jmax  = 81 K, the temperature ripple amounts to 48 K. For the AlSiC base plate results ΔT _jav  = 69 K and ΔT _jmax  = 90 K, the temperature ripple amounts to 42 K.

The Cu base plate module has a high thermal mismatch between Cu and AlN, therefore, in the viewpoint of high reliability only the other systems shall be considered. In the module without base plate we have a higher temperature ripple, in the AlSiC base plate module we have a lower temperature ripple, however at a significant higher temperature. Maximal temperature affects reliability as well as temperature ripple, for details on lifetime estimation see Chap. 12.

The used simplification of constant losses during t _on is not realistic in motor drive applications, in fact the on-state losses have a term proportional to sin²(ωt), the switching losses are proportional to sin(ωt). The result of the comparison, however, will be similar.

11.5 Parasitic Electrical Elements in Power Modules

Every power module contains parasitic resistance s and parasitic inductances causes by internal conduction tracks, as well as parasitic capacities provoked by parallel conductors separated by dielectric layers. Their influence is not negligible, especially during fast switching operation.

11.5.1 Parasitic Resistances

The significant contribution of external and internal leads to the total voltage drop in discrete packages was already addressed in Sect. 11.2. Figure 11.29 illustrates the evolution of package designs produced by International Rectifier (IR). Table 11.5 lists the characteristic parameters of these package types.

Fig. 11.29

Optimization of discrete package architecture concerning the reduction of parasitic resistance and induction, as well as the improvement of the thermal resistance, according to [Zhg04]

Table 11.5 Characteristic parameters of the package designs shown in Fig. 11.29 according to [Zhg04]

The substitution of wire bonds by a copper strap in the transition from the SO-8 package to the Copperstrap design reduces the parasitic resistance and the parasitic inductance. Since the progress in chip technology succeeded in reducing the on-state resistance to approximately 1 mΩ for a 40 V MOSFET, this package improvement was mandatory. The progress towards the Power-Pak housing is marked by a substantial improvement of the thermal resistance by implementing a solid copper base, which supplies an effective thermal path and at the same time represents the electrical drain contact. The ultimate progress was the development of the DirectFet package, which reduces the parasitic effects and the thermal resistance to a minimum.

The parasitic resistance in power modules is also considerable. For advanced power modules, the manufacturers often explicitly specify the parasitic resistance induced by the package in data sheets. Infineon indicates a value of 0.12 mΩ for the high performance power module FZ3600R12KE3, which is a 1200 V IGBT module with a rated current of 3600 A. Thus, the parasitic resistance implies an additional voltage drop of 0.43 V at the nominal current of 3600 A. The on-state voltage drop of the IGBT has a typical value of 1.7 V. Therefore, the package provokes roughly 20% of the total voltage drop. Other high current modules feature comparable values.

If the 36 IGBT chips rated 100 A each in the Infineon power module would be replaced by 75 V 100 A MOSFET chips with an on-state resistance R _DS,on of 4.9 mΩ, the voltage drop of the package would be in the same range as the voltage drop of the MOSFETs.

Even though the total parasitic resistance of a power module is an obstacle for power electronic applications because it generates additional losses and thus reduces the system efficiency, the consequences of internal parasitic resistances are even more severe, because they affect the static current distribution in high power modules with multiple parallel chips. This effect will be considered in more detail in the following simple example.

This simple model comprises 5 parallel diode chips with a rated current of 70 A each. The chips are soldered to a DBC substrate which is contacted to a heat sink by a thin layer of thermal interface material as shown in Fig. 11.14. The position of the cathode contact is on the left side, the anode contact is located on the right side of the substrate. The parasitic resistance of the Cu-layers on the DBC and of the wire bonds constitute an electrical network together with the (temperature dependent) forward voltage drop of the 5 diodes. With the material parameters and realistic assumptions on the geometry, the current distribution in this network can be solved with the boundary condition that the same voltage drop must occur for each current path.

In a first step, identical temperatures are assumed for all 5 diodes and the network is solved for 5 mm distance between the chips (Fig. 11.30a). Then the losses resulting from the individual currents through the diodes are inserted in an FEM model according to Fig. 11.30b and the calculated area-related average chip temperatures are determined in a second step. Re-inserting these temperatures into the network starts an iteration process which will converge against a thermal-electrical consistent solution for the given problem. The results are depicted in Fig. 11.31 (the lines are only drawn as a guide to the eye).

The solution for a distance between the chips of 5 mm, indicated by triangles, shows a variation of currents between 40 and 86 A while the temperatures vary between 115 and 150 °C with the maximum at the rightmost chip in Fig. 11.30a for the rated total current of 350 A. The main reason for this imbalance is the much smaller width of the anode current track on the DBC which leads to the maximum current and temperature for the chip at position 5.

Since the parasitic resistances between the chips are the root cause for the imbalance, a reduction of the resistances should improve the current distribution. This can be achieved by placing the chips closer together as illustrated by the second version in Fig. 11.30 with a distance of only 1 mm between the chips. However, this layout change will also increase the thermal interaction between the chips. Repeating the same iteration procedure as for the layout with 5 mm distance between the chips leads to the result also displayed in Fig. 11.31 (indicated by the circles). It shows, that the maximum current can actually be reduced to ~77 A. However, the maximum chip temperature rises to 160 °C at chip position 4 for this layout with reduced parasitic resistance.

Fig. 11.30

Simple model of five parallel diode chips with 5 mm distance between chips in top view (a) and cross section (b) and version with 1 mm distance (c) [Scn15]

Fig. 11.31

Thermal-electrical consistent solution of the current distribution and the temperature distribution of the models defined in Fig. 11.30 [Scn15]

For this simple model the paralleling of diodes was considered. These diodes exhibit a negative temperature coefficient of the forward voltage drop, which amplifies temperature imbalances, since the hotter chip will attract even more current. For paralleling IGBTs with a pronounced positive temperature coefficient at nominal current the impact of thermal coupling would be less pronounced.

Although the absolute values shown in Fig. 11.31 are related to the specific model assumptions, the general trend applies to every high power module design with parallel chips: Each design will always be a compromise between the conflicting requirement of minimized parasitic resistance and minimized thermal coupling between the parallel chips. Further reduction of the on-state voltage for future power chip generations will increase the impact of unbalance in parasitic electrical resistance.

This example shows that it is an important goal to reduce the parasitic resistance in power modules, especially for high current and low voltage modules. However, the internal parasitic inductance has an even greater impact on the performance of the package.

11.5.2 Parasitic Inductances

Every current lead is associated with a parasitic inductance . For the estimation of the magnitude of inductance, a rule of thumb applies for the inductance of current tracks:

$$ L_{par} \approx 10\,{\text{nH}}/{\text{cm}} $$

(11.13)

The inductance can be reduced by parallel arrangement of the plus and minus tracks; this technique is applied frequently in modern power modules. The module inductance is typically in the range of 50 nH for classical module designs. The more advanced packages, this value is reduced to 10–20 nH. These parasitic inductances affect the commutation circuit as shown in Fig. 11.32.

Fig. 11.32

Parasitic inductances in the commutation circuit

• L1 and L6 represent the inductances of the DC-link capacitors and of the current tracks to the DC-link.

• L2 is the inductance formed by the plus terminal and the current track on the substrate to the collector of the IGBT soldered to the substrate.

• L3 is composed by the bond wires on the emitter of the IGBT and by the current tracks on the substrate to the AC-terminal.

• L4 is synthesized by the current tracks from the AC-terminal to the cathode contact of the freewheeling diode, soldered to the substrate.

• L5 consists of the bond wires on the anode contact of the freewheeling diode and the track to the minus terminal, including the terminal itself.

• L8 represents the inductance of the load, which acts as the major current source during commutation. This inductance, as well as the series inductance of the AC-terminal L7, is not affecting in the commutation circuit. The effective internal parasitic inductances are all connected in series, so that they can be merged into a single module inductance L _pm .

$$ L_{pm} = L2 + L3 + L4 + L5 $$

(11.14)

The total parasitic inductance L _par is then given by the series connection of the module inductance with the DC-link inductances.

$$ L_{par} = L_{pm} + L1 + L6 $$

(11.15)

The impact of this parasitic inductance on the dynamic properties of a power module will be illustrated by two examples. In the first example, we will consider a frequency converter for a three-phase motor drive. This converter is formed by three IGBT half-bridge modules of the voltage class 1200 V with a nominal current of 800 A each.

The maximum DC-link voltage V _DC is 800 V and the parasitic inductance of each phase leg L _par is assumed 20 nH. The rate of current rise di_r/dt shall be 5000 A/µs. The voltage characteristic during commutation under these assumptions can be calculated by Eq. (5.72):

$$ V(t) = - V_{DC} - L_{par} \cdot \frac{{di_{r} }}{dt} + V_{tr} (t) $$

Evaluation of this equation delivers an over-voltage peak of 100 V. Therefore, the maximum occurring voltage would amount to 900 V, which lies safely within the specification limits of the power modules. Furthermore, it is a typical feature of IGBTs, that the voltage V _tr (t) is not exhibiting an abrupt cut-off, but rather decreases slowly after turn-on. Since V _tr (t) has the opposite polarity compared to the voltage spike generated by parasitic inductance, no voltage spike above 800 V can be detected in an actual measurement. An example is shown in Fig. 5.21.

The second example considers half-bridge modules in an integrated starter-generator application for a 42 V vehicle power system of an automobile. The MOSFET power switches have rated current of 700 A each and blocking voltage of 75 V. As before, the parasitic inductance is assumed 20 nH and the di_r/dt shall be 5000 A/µs. Again, the over-voltage peak generated by the parasitic inductance would be 100 V, resulting in a total maximum voltage of 142 V. In contrast to an IGBT , the voltage decay in a MOSFET is rather abrupt after turn-on, so that it does not assist to reduce the total over-voltage spike. The resulting 142 V spike is clearly exceeding the maximum blocking voltage of the MOSFETs!

These examples illustrate a general feature in power electronic applications: Systems with high currents at a low voltage are most sensitive to parasitic inductance. Additionally, the problem of symmetric current paths is more severe in these applications.

To investigate this problem further, a parallel configuration with 5 IGBTs and the associated freewheeling diode with 1200 V blocking capability on a single DBC substrate is considered (Fig. 11.33a). The positions of the load terminals are indicated. A schematic circuit diagram for this design is depicted in Fig. 11.33b. The current tracks on the substrate are represented by the inductances L1 to L9, whereas L10 to L15 are symbolizing the wire bond connections.

Fig. 11.33

(a) Realistic power circuit consisting of 5 parallel IGBT chips and one anti-parallel freewheeling diode chip (b) schematic circuit diagram showing the power devices plus the parasitic inductances formed by the current tracks

While the current path relevant for commutation from the terminals via IGBT3 contains only four parasitic series inductances, the relevant current path via IGBT1 contains eight parasitic series inductances. Since the values of the parasitic inductances are in the same order of magnitude for the given geometry, a factor of 2 can be assumed between the parasitic inductance for the two IGBTs. This will result in a pronounced dynamical unbalance in the current distribution of this circuit during commutation. Moreover, the parasitic inductances can lead to oscillations between the chips, which will be investigated in Chap. 14.

It is difficult to find a symmetrical arrangement for a multitude of parallel chips in a high current power module; the example in Fig. 11.33 is all in all one of the better solutions. In this context, designs combining a chip connected via a geometrically short current track with chips connected in parallel via geometrically long tracks are especially problematic. In induction measurements, the low parasitic inductance along the short path will dominate the result, while internally extensive differences generate a severe dynamical imbalance.

Solutions to this problem have been proposed [Mou02], which denote a substantial progress especially for applications with high currents at low voltages. Figure 11.34 shows an example. The elementary cell is a half-bridge configuration of two MOSFET chips. The function of the freewheeling diodes is adopted by the internal diode of the MOSFET switches. The design of the elementary cell was optimized by numerical simulation using a Fast-Henry-algorithm [Kam93], which allows to calculate the dynamical current distribution during high frequency commutation in the 3-dimensional model, with Skin-effect and eddy currents taken into account. The optimized cell design in Fig. 11.34a exhibits a parasitic inductance of 1.9 nH for a single elementary cell. By symmetrically paralleling 7 of these elementary cells and by connecting the DC-link bus bar as laminated metal sheets directly on top of the plus and minus terminals, a parasitic inductance in the sub-nH range was achieved. This module architecture is suitable for the application in an integrated starter-generator system as described in example 2 above.

Fig. 11.34

Advanced MOSFET half-bridge configuration (a) Elementary cell with a simulated parasitic induction of 1.9nH (b) Highly symmetrical circuit design with 7 elementary cells in parallel per half-bridge [Mou02]

11.5.3 Parasitic Capacities

Insulated substrates in a power module create a capacitor, which will also influence the dynamical characteristics of the power circuit, as illustrated in Fig. 11.35 for a simple construction.

Fig. 11.35

Parasitic capacities in a package with a diode chip mounted on an insulated ceramic substrate [Lin02]

The copper tracks on the substrate generate two capacities C _PA and C _PK connected to the ground contact, which is represented by the module case. The series connection of C _PA and C _PK is connected in parallel to the internal junction capacity of the diode. In more complex circuits, these capacities will also form capacitive coupling links to other parts of the circuit. The dimension of these capacities depends on the insulator material and the thickness of the insulating layer. Characteristic parameters are collected in Table 11.3, Sect. 11.3.

Since insulation layers of epoxy and polyimide have only a marginal thermal conductivity, but at the same time exhibit a very high breakdown voltage, layers of these materials are rendered very thin. This results in a high capacity per unit area and limits the applications for components with these insulation materials (i.e. IMS substrates ) for fast switching devices.

In an insulated TO-220 package, the cathode current contact features an area of 8 mm × 12.5 mm. Assuming a ceramic insulation layer of 0.63 mm thickness with a relative dielectric constant ε _r  = 9.8 delivers a parasitic capacity on the cathode side C _PK according to

$$ C_{PK} = \varepsilon_{0} \cdot \varepsilon_{r} \cdot \frac{A}{d} $$

(11.16)

The evaluation of this equation yields a parasitic capacity of 14 pF for the given geometry, for a thinner ceramic layer of 0.38 mm the value rises to 23 pF. If the diode used in this example is a GaAs Schottky diode DGS10-18A, then the (voltage dependent) junction capacity is specified at 100 V with C _j (100 V) = 22 pF [Lin02]. This value lies in the same range as the cathode parasitic capacity of the package. Therefore, the dynamic characteristic will not be determined by the junction capacitance alone, it will rather be modified by the external parasitic capacity.

However, as stated before, the parasitic capacity parallel to the junction capacitance is determined by the series connection of C _PK and C _PA . This diminishes the problem, since the area of the anode side current track is generally much smaller than the area of the cathode track. The total parasitic capacity C _PG parallel to the junction capacity is given by

$$ C_{PG} = \frac{{C_{PK} \cdot C_{PA} }}{{C_{PK} + C_{PA} }} $$

(11.17)

If C _PA is only 1/5 of C _PK , the total parasitic capacity parallel to the junction capacitance C _PG is only 1/6 of C _PK . This favorable condition is generally fulfilled in packages of the TO-family.

Now the example circuit is extended. In order to increase the blocking capability, two diodes in TO-packages are connected in series, while the geometry for each single diode is still in accordance with Fig. 11.35. The equivalent schematic circuit diagram for the extended example is depicted in Fig. 11.36.

Fig. 11.36

Parasitic capacities in a series connection of two TO-220 diodes [Lin01]

The parasitic capacity parallel to the junction capacity C _J1 of diode D1 is formed by C _PK1 in series with the parallel connection of C _PA1 and C _PK2 . With two identical packages and the assumptions of the relation of areas discussed above, the parasitic capacity parallel to C _J1 amounts to 6/11 C _PK1 or 0.54 C _PK1 .

The parasitic capacity parallel to C _J2 of diode D2 is composed by the small capacity C _PA2 in series with the parallel connection of C _PK2 and C _PA1 . This capacity calculates to 0.17 C _PK1 .

Therefore, the parasitic capacities form an asymmetrical dynamical voltage divider, which generates different voltages drops over the two diodes during high frequency switching processes. This example illustrates, that parasitic capacities can lead to unfavorable effects, which do not become obvious at the first glance.

If TO-package s without internal insulations are mounted on a common heat sink, external insulation layers like polyimide foils have to be applied. These external foils also establish parasitic capacities, which exhibit even higher values, according to Table 11.3.

Especially challenging are power modules for wide bandgap devices, e.g. SiC-MOSFETs. The device package also contains, besides the known chip internal capacities C _gs , C _gd and C _ds , the capacities formed by the substrate insulator layers, e.g. Al₂O₃ or AlN, which are displayed in Fig. 11.37b as C _σ+ , C _σout and C _σ- . Another point to consider is that C _σout is recharged with every switching event, and an undesired current is supplied into the heat sink. If the two L _σ and the C _σ+ , and C _σ− are unbalanced, they also generate a current into the heat sink [Fei15].

Fig. 11.37

Parasitic elements (a) In the chip (b) Switching cell parasitics. Figures from [Fei15]

While the presented simple examples can be evaluated by analytical inspection, real multi-chip packages with a variety of chips and current tracks exhibit a much higher complexity, which makes it almost impossible to investigate by an analytical approach.

The situation is actually even more complex, since parasitic resistances, inductances and capacitances, as well as the junction capacities of the power devices have to all be considered at the same time. Their interaction during dynamic switching processes can form resonant circuits, which can cause oscillations [Gut01]. This will be discussed in Chap. 14. Today, software tools like the Fast-Henry algorithm allow simulating the electrical characteristics of complex 3-dimensional systems in detail. The analysis and optimization of power modules with respect to parasitic effects is possible and necessary to increase the reliability of power electronic systems.

11.6 Advanced Packaging Technologies

Power semiconductor packaging has become a key technology for the progress of power electronic devices. There are four basic challenges to be met:

• 1. The current density in power devices is continuously increasing. Even today, the package related voltage drop in a power module accumulates to a considerable percentage of the total voltage drop at nominal current. Thus, improved architectures with a reduced electrical resistance of the load current paths are required.

• 2. The increasing power density requirement of advanced power electronic applications enhances the power density per unit area. This development demands progressive technologies to extract the heat generated in modern power module designs.

• 3. The physics of silicon semiconductor devices allows maximum junction temperatures up to 200 °C for selected applications. It can be expected, that MOSFETs, IGBTs and freewheeling diodes with a voltage rating of 600 V can be operated up to a maximum junction temperature T _j  = 200 °C after the necessary improvements of leakage current levels and of the reliability of the passivation . Wide bandgap devices on the basis of SiC and GaN are capable of even higher operation temperatures. In consequence, the reliability under extended temperature swings and extended maximum temperature must be ensured, especially with respect to active power cycles. The established standard module architectures are not capable to meet these requirements today; new materials and interconnection technologies must be developed.

• 4. The parasitic inductance s and capacities must be minimized or else controlled, so that they are transformed from undesirable obstacles into functional elements of power electronic circuits.

Finding a solution to these challenges is a task, which is intensively addressed by research and development groups all over the world. The ‘Center for Power Electronic Systems’ (CPES), a consortium of 5 universities and several industry partners in the USA, has proposed to replace the aluminum wire bonds by a copper foil, which provides a larger effective cross section at the top side chip contact [Wen01]. The interconnection between this foil and the contact metallization of the chip is achieved by a ‘dimple array technique ’, where only localized indentations in the foil are soldered to the chip. However, this technology has so far not been implemented in a series production and the expected increased lifetime during active power cycling has not yet been demonstrated.

The integration of the cooling system into the base plate has been proposed in order to improve the heat transfer of power modules. This concept eliminates the need for thermal interface materials between the base plate and the heat sink, which accounts for a considerable contribution to the total thermal resistance. The technique of integrating the cooling system into the DBC substrate goes even further [Scz00], because it eliminates the interface between the substrate and the base plate as well. The substrate serves as an assembly layer for the chips and as a heat sink while providing an electrical insulation, thus combining three functions in a single element. A drawback of this proposal is the comparatively small cross section of the cooling liquid channels, which is responsible for a high pressure drop in the cooling system. This makes the system vulnerable to pollution particles in the cooling system. Moreover, the reliability of such a high tuned cooling system is of crucial importance for the device operation: A transgression of the maximum heat extraction capability would lead to the formation of a vapor layer between the cooled surface and the liquid flow, which would result in an instantaneous dramatic increase in the thermal resistance of the system. The short time constant of such a highly efficient system will result in an abrupt junction temperature increase, which will damage or possibly destroy the semiconductor device. This reliability issue is common to all highly effective cooling systems, which are currently investigated on the basis of heat pipes or based on impingement cooling methods.

11.6.1 Silver Sintering Technology

A task of fundamental importance is the accomplishment of a sufficient power cycling lifetime at high maximum junction temperatures T _j . A very promising approach to reach this goal is the ‘low temperature joining technology’ (LTJ ). In this process, which is a diffusion sintering technique, a powder of silver particles is placed between the two surfaces to be joined. These surfaces require noble metal surface platings. An organic protection layer inhibits the silver particles to avoid diffusion of particles prior to the joining process. A heating process to approximately 250 °C during the application of a high pressure to the sinter interface dissolves this protective coating and activates the diffusion of the silver particles. This results in a densification of the powder layer to a porous rigid interconnection layer of high reliability [Mer02].

The properties of this interconnection layer are superior to solder interfaces in all parameters. The specific thermal conductivity of the sinter layer can be as high as 220 Wm⁻¹ K⁻¹ and is therefore almost a factor of 4 times higher than the thermal conductivity of a conventional SnAg3.5 solder layer. Together with a characteristic layer thickness of <20 µm, the sinter technology exhibits a reduced thermal resistance between the chip and the substrate compared to conventional solder layers of typically >50 µm thickness. The electrical conductivity is also improved due to the low specific electrical resistance of silver.

However, the major advantage of the silver diffusion sinter interface is the high melting temperature of the interconnection. This advantage can be illustrated by the concept of homologous temperature. Mechanical engineers use this concept to evaluate the reliability of an interconnection under mechanical stress. The homologous temperature is the ratio of the operation temperature divided by the melting temperature of the material in absolute temperature. Figure 11.38 displays the homologous temperature for a conventional SnAg(3.5) solder interface, a high temperature AuGe(3) solder interface and the silver diffusion interface, assuming an operation temperature of 150 °C.

Fig. 11.38

Homologous temperature for a conventional solder interface SnAg(3.5) T_liquidus = 221 °C, a high melting solder interface AuGe(3) T_liquidus = 363 °C and the silver diffusion interface Ag T_liquidus = 961 °C for an operation temperature of 150 °C

Mechanical engineers consider interconnections operated below 40% of the homologous temperature as mechanically stable, between 40 and 60% as operated in the creep range, sensitive to mechanical strain, and above 60% as unable to bear engineering loads. Figure 11.38 illustrates clearly, that even solder interfaces with a liquidus temperature of 363 °C have a limited reliability for an operation temperature of 150 °C, while the silver diffusion technology can be expected to be reliable under mechanical stress.

Another advantageous feature of the silver diffusion technology, which might be overlooked at the first glance, is the absence of a liquid phase during the connection process. In a solder process, the solder interface passes through a liquid phase, while the temperature exceeds the liquidus temperature. During this phase of the solder process, the chip swims on a liquid film with the consequence of a series of fundamental problems:

• The chip might shift or turn out of its desired position. Solder jigs or solder stop layers are necessary to minimize this effect. Both countermeasures require a considerable margin, so that the position accuracy in a solder process is limited.

• The solder layer can exhibit a wedge-shape thickness distribution due to a variation of the surface wettability with considerable impact on the thermal resistance and thus on the reliability of the solder interface.

• Solder voids cannot be eliminated completely in an industrial series production.

Since the silver diffusion technology does not comprise a transition through a liquid phase, these problems well known from solder technologies are eliminated. In a well-controlled silver diffusion process, the chips are perfectly aligned and the interface has a homogeneous thickness without any large scale voids.

The diffusion sinter technology was adapted to the assembly of modern power devices like IGBTs, MOSFETs and freewheeling diodes in the middle of the 90s [Kla96]. Further process improvements verified that the simultaneous connection of multiple (different) power chips can be achieved in a single process step, which makes this technology compatible with modern series production [Scn97]. In 2008 the first commercially available series power module was introduced, which contains not a single solder interface [Scn08]. This module design combines the silver diffusion technology with the pressure system technology and spring contacts.

Experimental results confirm the expected high reliability under extreme power cycles. A power cycling test with ΔT _j  = 130 K survived 30,000 cycles, which exceeds the estimated lifetime for classical base plate modules derived from an extrapolation of the LESIT curve (Eq. (12.2)) by more than a factor of 20 [Amr05]. This technology seems to be very promising even for maximum operation temperatures up to 200 °C – as was investigated in active power cycling test with ΔT _j  = 160 K [Amr06] – which allows to extend the application of power modules to challenging environments, e.g. in the motor compartment of hybrid automobiles.

The silver diffusion sinter technology has the potential of replacing even the wire bonds by connecting a silver foil to the top side chip contact as shown in Fig. 11.39. This eliminates another weakness in the classical module architecture: the aluminum wire bond. This improvement reduces the parasitic resistance and inductance of the top side chip contact and further enhances the power cycling reliability [Amr05].

Fig. 11.39

Silver diffusion sinter technology applied to the bottom and top side chip contact, eliminating the traditional solder interface and replacing the wire bonds with a silver foil. Source TU Braunschweig

11.6.2 Diffusion Soldering

Another method to improve the reliability of the chip-to-substrate interconnection is the diffusion soldering technique. The principle is based on a process called ‘Transient Liquid Phase Bonding’, which has been applied in industry since many years mostly for Ti alloys [Mac92]. By applying this principle to SnCu alloys the homologous temperature of the chip interconnection can be significantly increased.

In a first step a thin eutectic alloy of Sn and Cu is liquefied at a temperature of 227 °C. The surfaces of the chip and the substrate are equipped with Cu layers so that copper is diffusing into the liquid solder and will form intermetallic phases, see Fig. 11.40. Close to the copper surfaces a copper rich phase Cu₃Sn with a melting temperature of 676 °C will form followed by a layer of a Cu₆Sn₅ phase with less copper content and a melting point of 415 °C. In the following diffusion step a high temperature will be maintained and the intermetallic phases will grow towards the center of the solder layer and progressively consume the Sn content in the eutectic alloy. Finally, the fronts of the Cu₆Sn₅ phases growing from both sides will meet in the center and the original solder alloy will be almost completely transformed into intermetallic phases with a melting point of at least 415 °C as shown in Fig. 11.41.

Fig. 11.40

Equilibrium phase diagram for Sn–Cu alloys [Smi76]

Fig. 11.41

REM image of a cross section of the interconnection obtained by diffusion soldering [Gut10]

To maintain a reasonable diffusion time of several minutes, the bondline thickness must be in the range of 10 µm. This restricts the acceptable tolerances for the chip and the substrate surfaces. To mitigate this limitation a modification of this process was proposed: By dispersing Cu particles in the eutectic solder alloy, these particles could serve as additional sources for the diffusion of copper so that much thicker interfaces could be realized without increasing the diffusion time. The problem of this process however is the homogeneous dispersion of the Cu particles. If these Cu particles agglomerate in the paste of eutectic alloy, the intermetallic phase grow will not be evenly distributed. In the worst case, agglomerated Cu particles can even form vertical pillars between the chip and the substrate and thus produce voids in the interconnection layer.

However, if chips with a Cu backside metallization are available and the specific process requirements a met, diffusion soldering can establish chip-to-substrate interconnections with a melting point of 415 °C and above, while maintaining the process temperature in the range of 250 °C. The increase of lifetime under thermo-mechanical stress is expected lower than the increase for Ag diffusion sintering, but diffusion soldering avoids the high pressure in the range of 40 MPa required for silver sintering.

Diffusion soldering in industrial scale was presented by [Gut10, Gut12]. Also a new solder process substrate to base plate is reported in [Gut10]. The new solder layer contains vertical intermetallic phases with high melting temperature (Fig. 11.42).

Fig. 11.42

Substrate solder layer containing vertical intermetallic phases. Figure from [Gut10]

At temperature swings and the given CTE mismatch between the neighboring layers, it will be difficult for a crack to cross laterally through the harder vertical intermetallic phases. Therefore, crack propagation is strongly slowed down. This was confirmed by a power cycling test with high temperature swing of the base plate of ΔT of 100 K with aim to stress the interconnection base plate to substrate. The expected increase in power cycling capability by a factor of 2.5 to 3 was confirmed [Hen10].

11.6.3 Advanced Technologies for the Chip Topside Contact

Aluminum wire bonds with diameters between 300 and 500 µm are established for more than 30 years as topside chip contact in standard MOSFET or IGBT power modules (see Fig. 11.13). A wedge-wedge ultrasonic bonding machine can establish a single wire connection from the top side chip metallization – conventionally an approx. 4 µm Al layer – to the substrate current trace within fractions of a second. A single Al wire bond of 10 mm length can conduct currents of 18 and 50 A for a diameter of 300 and 500 µm, respectively, due to the high heat extraction capability of the standard power module mounted on an efficient heat sink.

The wire bond process is highly flexible and can be adapted to different layouts and design changes by a simple software update. This great advantage is accompanied by several aspects of concern: The wire bond contributes to parasitic resistance and inductance of the module, it is limited in current capability and lifetime – as will be discussed in more detail in Sect. 12.7.2 – and the wires will act as fuses at extreme over-currents, which will result in arcing and in consequence in an explosion with often considerable damage in the power electronic system.

In the first decade of this century, two driving factors have increased the demand for an improvement of the chip topside contact. Firstly, the increasing current density of the devices requires an increasing number of Al wire bonds. For modern low-voltage MOSFETs it is already very difficult to place the required number of Al wire bonds on the source contact. Secondly, the extension of the maximum junction temperature from 150 to 175 °C and in the future to even 200 °C requires a lifetime increase of the modules. The increased operating temperature range can only be exploited, if the lifetime is increased accordingly. As a rule of thumb, each 25 °C increase in operation temperature requires a lifetime increase by a factor 5, so that the lifetime of the standard module technology must be enhanced at least by a factor 25.

Cu Bond Wires

Cu bond wires were introduced by Infineon [Gut10]. Cu exhibits high yield strength of 140 MPa compared to Al with 29 MPa. Further, the CTE of Cu is with 16.5 ppm/K much better matched to Si (2 ppm/K) than Al with 23.5 ppm/K. Cu has higher electrical and thermal conductivity than Al. The power losses P _bond in a bond wire with length l are given by

$$ P_{bond} = R_{bond} \cdot I^{2} = \rho \cdot \frac{l}{A}I^{2} $$

(11.18)

For the same wire length and diameter, the current for same P _bond increases by $\sqrt {{{\rho_{Al} } \mathord{\left/ {\vphantom {{\rho_{Al} } {\rho_{Cu} }}} \right. \kern-0pt} {\rho_{Cu} }}}$. Special soft Cu bond wires were developed by soft annealing, leading to low deformation resistance [HER15], the specific resistance increases slightly compared to bulk Cu and is given as ρ _Cu  = 1.8 µΩ cm. Cu has compared to Al a higher melting temperature. Finally, the fusing current per wire is increased, in [Her12] an increase by a factor of 1.25–1.27 is given when comparing Cu to Al. For same wire diameter and length, a 50 K lower temperature in the loop of the bond wire is calculated for Cu compared to Al [Sie10].

A cross section of a Cu bond wire and a substrate with Cu bonds is shown in Fig. 11.43.

Fig. 11.43

Cross section of a Cu bond foot (top), view of a substrate equipped with dies with copper metallization and Cu bond wires. Figure from [Gut10]

Cu wire bonding requires, compared to Al wire bonding, higher bonding forces, significant higher ultrasonic power and modified cutting tool concepts. A comparison of bond parameters is made in Fig. 11.44. Cu bonding is not compatible with Al-metallized device surface, since the high power and applied force could cause cracks in the semiconductor body. Additionally, IGBTs and MOSFETs have a cell structure containing a thin SiO₂ isolation layer between gate-emitter resp. gate-source, which is sensitive against too high local mechanical load. Cu wire bonding requires a Cu metallization of sufficient thickness, 5–50 μm are mentioned in [Her12]. Cu metallization is already known from the fabrication of microelectronic devices in which, for the submicron structures, high current densities occur. The metallization needs diffusion barriers to silicon to avoid contamination. The metallization technology was successfully transferred from microelectronics to power electronics.

Fig. 11.44

Comparison of bond parameters for Al and Cu. Figure adapted from [Bec15]

Modules with Cu wire bonds can reach very high power cycling performance, the bond wire is no longer limiting the lifetime.

Cu exhibits compared to Al a higher thermal capacity. Therefore, it is of advantage to make the Cu layer in a significantly higher thickness than 4 µm as usual for Al metallization. However, due to the thermal mismatch to silicon this can lead to wafer bow, which is an obstacle for fine pattern of metallization. The challenge is more exposed for thin wafer technology. And in same time, 300 mm wafer technology for IGBTs is coming up. Therefore, several trade-offs have to be taken into account.

Bond Buffer Technology

Since only some dies from special manufacturers are available with Cu metallization, the bond-buffer technology was introduced by Danfoss. Here, a thin Cu plate (“bond buffer”) is attached on the topside of the die with silver sintering. Figure 11.45 shows the structure of the so-called “DBB-technology”. Beside silver sintering on the topside, this interconnection is also applied at the bottom side and replaces the chip solder layer.

Fig. 11.45

Bond buffer technology. Figure from [Rud12]

The process just requires a noble-metal surface of the chip metallization. If this is applied, different dies from several manufacturers can be used. The Cu bond process can be executed with desired ultrasonic power since the cell structure is effectively protected. High power cycling capability is to be expected.

The structure gains advantage in thermal resistance and thermal impedance. The bottom side thin silver sinter layer improves the thermal resistance compared to solder layers. The bond buffer and Cu bond wires introduce additional thermal capacitance close to the chip which reduces Z _th for short time loads, especially at pulse duration of 10 ms and below [Rud12].

The thickness of the Cu buffer, however, cannot be increased too high, otherwise cracking caused by high thermal mismatch in the topside metallization will occur during temperature cycling or power cycling. In contrast to Cu-metallization, the bond buffer foil will not cover the complete active area of the device. At very short overload events, such as short circuit with duration of 10 µs or lower, these cells have no energy storage buffer on top and will fail first.

Al-clad Cu Wire Bonds

With Al-clad Cu wires it is intended to combine the superior electrical and thermal characteristics of Cu with the advantage of mass production of the Al wire bond process [Dal06]. Figure 11.46 shows an example of a 300 mm wire. The Cu core diameter amounts to 230–250 µm, the Al coating layer to 25–35 µm.

Fig. 11.46

Cross section of an 300 µm Al-clad Cu wire bond in (a) radial and (b) longitudinal direction. Figure from [Sct12]

During the bonding process, an Al to Al ultrasonic welding interconnection is established, therefore similar failure mechanisms under repetitive thermal load as for pure Al wires could be expected. However, the effective CTE of the wire bond is reduced and together with the lower electrical resistivity and the enhanced thermal conductivity, the crack initiation and propagation should be reduced. In fact, a significant increase of the power cycling capability was shown in [Sct12]. Figure 11.47 is showing the results.

Two types of cladded wires are compared in Fig. 11.47 with homogeneous Al bond wires. The type “hard” with hard Cu core shows the best power cycling results. It can be used for diodes with Al topside metallization. The type “soft” with soft-annealed Cu core lowers the risk of damage in sensitive devices with cell structures on topside and can be used for IGBTs. The power cycling tests in Fig. 11.47 have been executed with a “solder-free” package where Ag sinter layers are applied which are not limit the power cycling capability.

Fig. 11.47

Comparison of power cycling results of bond wires: yellow square Al-wires (lower line), red square Al-clad, hard Cu, green circle Al-clad, soft Cu

Even if the number of cycles to failure with the soft-annealed Cu is lower compared to “hard” Cu, it is a significant progress.

11.6.4 Improved Substrates

Aluminum oxide and Aluminum nitride substrates are established. With improvement of the die interconnection layer and the topside contact technology, the substrate will become the next limiting factor. Standard and new ceramic substrates are compared in Fig. 11.48. The parameters are given in Table 11.6.

Fig. 11.48

Comparison of temperature cycling capability of ceramic substrates with both-side Cu layers. Temperature swing −55/+150 °C. Figure from [Goe12]

Table 11.6 Characteristic parameters of the substrates in Fig. 11.48

The so-called HPS-substrate (high power substrate) consists of Al₂O₃ with 9% ZrO₂. Its standard thickness amounts to 0.32 mm [ELE09]. In Fig. 11.48 the temperature cycling capability of the different substrates is compared. AlN shows the weakest cycling capability, since in AlN conchoidal fractures in the ceramics occur [Dup06]. Al₂O₃ reveals a superior cycling lifetime, next HPS exhibits double number of cycles compared to Al₂O₃. Si₃N₄ is possible in two production processes. One is coating to allow application of the usual direct copper bonding process, the other is active metal brazing (AMB) which is a type of high temperature active soldering using AgCu alloys containing 1.5% Ti. Already in the coated version, Si₃N₄ shows a very high stability under temperature cycling. In the AMB version, it offers an excellent temperature cycling capability. For cycles from −30 to 180 °C, 780 cycles were executed without failure [Dup06]. In the results shown in Fig. 11.48, 5000 cycles were applied and no weakness occurred. Therefore, with this substrate even an increased thickness of Cu layers is possible, e.g. 400 or 500 µm. This leads to a high current capability of the substrate, and also to a very good head spreading effect [KYO05].

It is pointed out in [Miy16] that fracture toughness is the decisive parameter for the high stability of Si₃N₄ AMB, and the temperature cycling capability does not depend on flexural strength.

Beside Cu-metallized substrates, shown in Fig. 11.48, also Al-metallized substrates are possible. The Al layers are covered with a Ni film or a Ni–Au film to allow for soldering. Al has a much lower yield stress (30–35 MPa) compared to Cu (85–100 MPa), and also a much flatter plastic characteristics [Dup06]. A high temperature cycling capability for cycles between −55 and +125 °C was shown. The disadvantage is a higher thermal resistance due to the lower thermal conductivity of Al. Further, it must be taken into account that Al layers show the effect of reconstruction, which can be an obstacle for power cycling capability. Reconstruction of metal layers will be discussed in Sect. 12.7.2

11.6.5 Advanced Packaging Concepts

The advanced packaging concepts implement the new technologies introduced in previous sections into products. Several solutions focus on different aspects of package improvement.

Mold Modules With Strong Heat Spreading

The Mitsubishi mold module has a top side contact soldered to a Cu lead frame [Mot12]. The architecture shown in Fig. 11.49 is named as DLB technology (Direct Lead Bonding). The module is encapsulated with epoxy-based mold compound as known from the TO-family.

Fig. 11.49

Mitsubishi mold module, DLB technology. Figure from [Mot12]

As potential separation a so-called TCIL-layer (Thermally Conductive Insulation Layer) is used, which contains a thin laminated Cu-foil on the bottom side. Since the thermal conductivity of organic insulators is significantly lower than that of ceramics, a thick Cu layer is located above the insulation layer for lateral heat spreading, increasing the area for vertical heat transport. It is claimed that the thermal resistance is comparable to modules using AlN ceramic substrates [Mot12].

The Fuji Green Line technology is based on a Si₃N₄ substrate which is connected on both sides with a 1 mm Cu layer, see Fig. 11.50. The thick Cu layers act as effective heat spreaders, and the thermal performance is supported by the high thermal conductivity of Si₃N₄. The thermal impedance can be strongly reduced at medium time constants [Hor14].

Fig. 11.50

Fuji Green Line module. Figure from [Hor14]

On top side the semiconductor die is connected with Cu pins to a PCB, the whole module is encapsulated with an epoxy based mold compound.

An FEM-simulation in [Bec15] compares both package concepts using the same silicon die 10.6 mm × 10.6 mm. A thermal foil of 70 µm (2 W/m/K) to the heat sink with heat transfer coefficient of 5000 W/(m²K) is assumed in all cases. The reference is the Al₂O₃ based module from Table 11.1, with 0.38 mm Al₂O₃ ceramics, chip solder of 100 µm, soldered with thick solder 500 µm to a base of 3 mm (Fig. 11.51).

Fig. 11.51

Comparison of thermal impedance for standard modules and modules with strong heat spreaders. Figure from [Bec15]

At small time constants between 0.01 and 0.1 s, there is a strong improvement of the new packaging concepts. Also an improvement in the static thermal resistance is visible, most prominent in the Fuji green line concept. This is a result of the high thermal conductivity of the Si₃N₄ ceramics with the thick Cu layers on both sides. Also the strong heat spreading by two 1 mm Cu layers above the low thermal conductive layer to the heat sink is very effective to transfer the heat flow.

The SKiN Technology

The SKiN technology was presented by Semikron in [Bel11]. As shown by the schematic cross section in Fig. 11.52, the wire bonds are replaced by a flexible circuit board which is connected to the top metal layer of the chips by an Ag diffusion sinter interface. The chip-to-substrate as well as the substrate-to-heat sink interconnection is formed by diffusion sintering. This technology not only eliminates the solder layers and wire bonds known as the weak elements in the reliability chain of classical module design, it also replaces thermal interface materials (TIM) required between the module and the heat sink in the classical design by a high reliable diffusion sinter connection. All interconnections are realized by silver sinter technology: die topside, die bottom side and substrate to cooling plate.

Fig. 11.52

SKiN technology. Figure from [Scn12]

On the bottom side a pin fin cooling plate is used, named as “heatsink” in Fig. 11.52. The topside chip contact layer is part of a flexible circuit board consisting of two metallization layers, one on each side of a polyimide foil. The bottom metallization transports the load current and is called ‘power side’. The selected layer thickness is in the range of 100 μm. For the top side metallization referred to as ‘logic side’, a layer thickness of 35 μm is sufficient. This layer distributes the control and sensor signals. Vias in the flexible circuit board are connecting the gate contacts on the power side to the logic side as shown in Fig. 11.52. Additional SMD components can be assembled on the logic side in close proximity of the chips.

The SKiN technology has demonstrated a high power cycling capability. With more than 3 million cycles at ΔT _j  = 70 K, it enhanced the power cycling lifetime by a factor of 40 related to state-of-the-art industrial modules.

While the afore presented packaging concepts are designed to improve the packaging of Si devices, they are not sufficient to exploit the capabilities of progressive wide-bandgap devices. Fast switching SiC and GaN devices allow to considerably increase the switching frequency, but this requires a substantial reduction of the package parasitic induction. Investigations with 1200 V SiC-MOSFETs implemented in industrial power module packages have shown, that either pronounced voltage oscillations reduce the maximum DC link voltage or that higher gate resistors are required to reduce the switching speed of the devices.

A proposal for a package design with lower parasitic inductance is the strip line concept from Infineon [Bor13]. The arrangement of multiple pairs of DC+ and DC− contact in close proximity results in a module stray inductance below 7nH (Fig. 11.53).

Fig. 11.53

Low inductive package with strip line concept. Figure from [Bor13]

An advancement derived from the SKiN technology was applied to build a prototype module with a commutation stray inductance of about 1.4 nH [Bel16]. As shown in Fig. 11.54, the flex layer concept was extended to conduct DC− on the topside and DC+ on the bottom. Spring elements are implemented to establish a low profile contact between the flex layer and a PCB or laminated bus bar.

Fig. 11.54

Low inductive package derived from SKiN technology. Figure from [Bel16]

As mentioned at the beginning of Sect. 11.6, there are four basic challenges to be met:

• Low electrical resistance

• Efficient heat extraction

• High-reliable interconnections

• Minimized parasitic inductances and capacities.

New architectures face these challenges and show significant progress. The mold modules with strong heat spreading (Figs. 11.49 and 11.50) significantly improve thermal impedance and thermal resistance junction to case. The modules with pin-fin base plate (Fig. 11.52) significantly improve the thermal resistance junction to ambient [Hen10]. In the .XT technology from Infineon, Cu bond wires and diffusion soldering is applied. Further solutions are in research and development. The presented systems in this overview should be taken as examples and not as a complete list of innovative concepts.

For evaluating potential improvements in progressive packaging technologies, it is inevitable to consider the complex interdependency of single optimizations with respect to the performance of the complete system. Especially the impact of parasitic influences cannot be omitted. This aspect will be addressed in more detail in Chap. 15.