Testability design or design for testability (DFT) implies adding circuits within a test object to make it easier to test. With advances in VLSI, it is basically the increasing inaccessibility of the internal circuits that makes testing more and more difficult and causes testing costs to be an ever-growing portion of a product’s total costs. DFT techniques are valuable methods for helping solve the growing test problem. The cost is the increased silicon circuit area to accommodate the hardware overhead and potentially reduced circuit performance.
Testability design DFT design Design for testability Scan design Pseudo-random pattern test Ad hoc methods Built-in self-test
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N. Weste, D. Harris, Principles of CMOS VLSI Design – A Circuits and Systems Perspective, 4th edn. (Addison-Wesley, Reading, 2010)Google Scholar
H.T. Nagle, Design for testability and built-in self-test. IEEE Trans. Ind. Electron. 36, 129–140 (1989)CrossRefGoogle Scholar