PCM Array Architecture and Management

Abstract

This chapter discusses architectural solutions and cell management algorithms for a large PCM array. The “large” attribute is fundamental in the architectural definition, as the only cell that is suitable for a high-density array is the one where the selector size matches the size of the memory element. Due to the relatively high PCM cell operating currents, a bipolar junction transistor is the selector of choice for the PCM cell, offering the best current density in a small footprint among other devices. The use of a BJT selector needs a special care compared, for example, to an MOS selector, as the BJT base current is affecting substantially the array biasing. At the highest current density used in program operations, the BJT gain drops, and a large portion of the bit line current is transferred to the word line; for this reason in the chapter, the BJT is often referred to as a “diode” even though a fraction of the cell current is still sinked by the collector node. Reference for technology platform on which this study is based can be found in Servalli (IEDM Tech Dig).

On top of the array definition and biasing, the chapter offers an insight on the embedded algorithms used to get the maximum performance from the array and meet the reliability targets for the product. A few notes on embedded ECC and permanent repair storage (fuses) close the subject.