Characterization of a Sub-electron Readout Noise VGA Imager in a Standard CIS Process

Abstract

In the previous Chapter, we demonstrated that sub-electron read noise performance can be achieved, in a standard CIS process, at room temperature by optimal design. The design optimization included, for the first time, the choice of a thin oxide PMOS SF. These measurements gave promising results but on a small number of isolated pixels.

In the previous Chapter, we demonstrated that sub-electron read noise performance can be achieved, in a standard CIS process, at room temperature by optimal design. The design optimization included, for the first time, the choice of a thin oxide PMOS SF. These measurements gave promising results but on a small number of isolated pixels. This chapter presents the first implementation, in a standard process, of pixels with thin oxide PMOS SFs in a full VGA (640H$\times$480V) image sensor. The proposed imager features an input-referred noise histogram ranging from $0.25\,\text {e}^-_{\text {rms}}$ to a few $\text {e}^-_{\text {rms}}$ and peaking at $0.48\,\text {e}^-_{\text {rms}}$. In the mean time, it features an improved pixel layout leading to a pitch of $6.5\,\upmu \text {m}$, a dynamic range of 82.5 dB corresponding to a full well capacity of $6400\,\text {e}^-$ and a frame rate up to 80 fps. This imager crosses the bridge between highly sensitive low-light CIS and conventional imagers. It demonstrates the efficiency of the proposed design level noise reduction technique that can be easily combined with the process optimizations mentioned in Chap. 5 for even more noise reduction.

This chapter presents, in the first section, the overall architecture of the imager as well as its most important blocks. In the second section, a detailed characterization of the proposed imager with a description of the measurement methods are presented. The test results are discussed in the third section.

Fig. 7.1

Overall architecture of the proposed image sensor

7.1 Chip Architecture and Circuit Design

7.1.1 Imager Architecture

Figure 7.1 shows the overall architecture of the imager. It is a rolling shutter CMOS image sensor with 640(H)$\times$480(V) array of the newly proposed 4 T pixels with standard CIS PPDs. A row control mixed signal block generates for each line of pixels the reset (RST), transfer (TX) and selection (RS) signals (Fig. 7.6). The row control block also allows the control of the integration time. Each column of the pixels array is connected to a closed loop gain amplifier introducing gain and limiting the bandwidth. A mixed signal analog multiplexing block made of shift registers, voltage level shifters and analog switches is implemented at the output of the column-level amplifiers. It allows to choose between an analog or digital output. In the digital readout mode, each column-level output is simply connected to the input of a 10 bits single-slope ADC (SS-ADC). All the columns are read in parallel. In this configuration, the imager operates at 80 fps. In the analog readout mode, the shift registers and analog switches connect the columns to the analog output. In this case, the columns are read one after the other. The analog readout mode is important for proper characterization of the pixels. In this mode the frame rate is 640 times slower but the column and pixel readout time remain the same.

Fig. 7.2

Schematic of the proposed pixel (a) and a layout view of the neighboring pixels (b)

7.1.2 Pixel Design and Layout

The pixel design has been presented in the previous chapter. This section addresses the layout optimization. A minimum distance is imposed between the n-well and the neighboring NMOS and PPD. Also, a minimum distance between thin oxide and thick oxide transistors has to be fulfilled. In order to address these issues, an optimized layout still filling all the standard design rules is proposed. The optimization relies on putting the maximum number of transistors in the same n-well and keeping this latter away from the PPDs. Figure 7.2b shows the proposed layout of neighboring pixels. The repeated pattern of the pixels array consists of two symmetrical pixels sharing a common n-well with the two SFs and RSs. Inside the N well, a common thin oxide area contains the two SFs. This compact layout results in a fill factor of 40% with a pixel pitch of $6.5\,{\upmu }\text {m}$ compared to a pitch of $6.5\,{\upmu }\text {m}$ in the chip presented in the last chapter.

7.1.3 Column-Level Amplifier

The noise reduction starts by implementing enough column-level gain in order to minimize the noise contribution of the next stages, limiting consequently the noise analysis and optimization to the in-pixel SF stage, the current source of the SF and the column-level amplifier.

The thermal noise originating from the SF stage and column-level amplifier is reduced using a proper design of the SF current source and bandwidth control obtained with high column-level amplification [1]. Simulation results from [2] show that thermal noise originating from the SF stage, the column-level amplifier and the current source can be reduced to about $0.2\,\text {e}^-_{\text {rms}}$ if the bandwidth is limited to 265 kHz. Thermal noise can also be reduced using CMS at the end of the readout chain [3,4,5] but at the cost of additional circuitry when implemented in the analog domain and multiple analog-to-digital conversions when implemented in the digital domain. It has been shown in [1] that the input-referred thermal noise can also be reduced by increasing the conversion gain of the pixel. In this work we chose to perform a simple CDS for a faster readout. The bandwidth of the readout chain is roughly inversely proportional to the product of the column level gain and the load capacitance of the column level amplifier [1]. It has been set to 265 kHz with a gain of 64 in order to make the thermal noise lower than the 1 / f noise (below $0.3\, \text {e}^-_{\text {rms}}$). Figure 7.3 shows the simulated input referred thermal noise of the readout chain as a function of its bandwidth which is tuned using different combinations of the column-level gain and the load capacitance. It also indicates the estimated framerates achievable for each bandwidth. For large readout chain bandwidths, the framerate becomes limited by the time required by the ADC to convert and shift the data to the output which is about $10\,{\upmu }\text {s}$. At about 80 fps, the low frequency noise of the readout chain becomes the dominant noise source.

The 1 / f noise is dramatically reduced by the AZ and CDS or CMS. However, it remains the dominant noise in the readout chain [2, 3]. The critical transistors of the column-level circuitry can be designed to have gate sizes large enough to make their contribution to the total 1 / f noise of the readout chain negligible compared to the in-pixel SF’s. Thus, in a conventional low noise CIS readout chain, with column amplification, bandwidth control and careful design, the 1 / f noise originating from the in-pixel SF remains the dominant noise source.

Fig. 7.3

Simulated input referred thermal noise as a function of the readout chain bandwidth set by the column level amplifier with the estimated framerates achievable for the presented VGA imager

Fig. 7.4

Schematic of the column-level amplifier

Figure 7.4 shows the schematic of the column-level adjustable gain amplifier. The closed-loop gain is set by the ratio of the integrating and feedback capacitors. The feedback capacitors can be switched in order to change the gain between two levels: $\times$1, for high dynamic range in normal light conditions and $\times$64 for low light conditions. The open-loop gain is provided by an OTA. For the OTA design and layout, the priority is given to the noise constraint. The dynamic range is not critical since the voltage swing at the output of the pixel is not higher than 1.5 V. A single-ended structure is used because it involves half the number of noisy transistors compared to a differential one. Differential amplifiers are certainly better at rejecting any common mode noise (e.g. noise coming from the substrate and power supply) but at the cost of more noise and more power. Indeed, in the case of an operational transconductance amplifier (OTA) such as the one used in this amplifier, the differential structure requires to duplicate the circuit branch resulting in twice the power consumption and twice the thermal noise excess factor for achieving the same transconductance. In order to achieve low noise and to stay within our power budget, we have chosen a single ended implementation. The noise originating from the power and bias sources is reduced on-board by using power filters. Regarding the area, it is mainly set by the input and feedback capacitors especially for high gains. Hence, a differential topology would occupy about the same area but, as explained above, with the penalty of double power and noise. The situation would be even worse for a fully differential amplifier (differential input differential output) since it would generate twice as much noise, power and area compared to the single ended implemented in this work. The high closed-loop gain of 64 requires a large open-loop gain hard to achieve with a simple single ended amplifier. It is known that cascode structures provide much higher gain with a negligible noise contribution of the cascode transistors. Hence, a fully cascoded single-ended amplifier is used. In order to make the 1 / f noise contribution of the column-level amplifier negligible compared to the one originating from the pixel, the transistors of the OTA have gate areas more than 10 times larger than the SF. The charge injection of the AZ switch can reduce considerably the output voltage swing of the amplifier in the high column-level gain mode. In order to reduce that charge injection, dummy devices with a proper sizing are used in order to compensate the charge injected by the main NMOS switch.

Fig. 7.5

Block diagram of the SS-ADC of two neighbouring columns

Fig. 7.6

Timing diagram of the proposed readout chain

7.1.4 Column-Level SSADC

Figure 7.5 shows the schematic of two neighbouring column-level SS-ADCs. A double stage comparator is used to reduce the offset [6]. Figure 7.6 shows the timing diagram of the whole readout chain. After the reset of the SN, the auto-zeros of the consecutive column-level amplifier and comparators are opened sequentially in order to minimize the impact of charge injection [7]. Then the charges are transferred to the SN and the voltage at the input of the comparator is equal to the difference between the transfer and reset levels. The ramp is then activated together with the counter. Shift registers are used in order to memorise the 10 bit code once the output of the comparators is high. The CDS time is defined by the time between the opening of the AZs and the moment when the output of the comparator is high. During the readout of the next line, the 10 bit codes of all the column-level registers are shifted horizontally to the digital output.

Fig. 7.7

Chip micrograph showing the main design blocks of the imager

7.1.5 Physical Implementation

The chip has been fabricated in the same process than the pixels presented in Chap. 6, namely, a 180 nm CIS process with 4 metal layers, resulting in a chip area of 5 mm$\times$5 mm. The analog parts of the chip are powered with a 3.3 V source and digital parts with a 1.8 V. Figure 7.7 shows a chip micrograph locating the main design blocks. The VGA pixels array meant for a front side illumination occupies an area of 4.16 mm$\times$3.12 mm. Standard PPDs were used in the pixels array and the area between the even and odd pixels (Fig. 7.2b) occupied by the in-pixel transistors is covered by a metal layer (Fig. 7.8).

Fig. 7.8

The designed PCB and the assembled optical objective used to test the presented image sensor

7.2 Test and Characterization

7.2.1 Experimental Setup

In order to test the presented chip, the latter was packaged in a PGA 144. A PCB has been designed to generate the different bias voltages and power supply ranging from 0 to 3.3 V, control the shape of the (TX) signal and generate the ramp of the SS-ADC. The chip is mounted on the board through a socket over which an optical objective is assembled. The board is powered with an external $\pm 5$ V source and encompasses power supply filters for low noise requirements. The board is connected to a PXI rack with two FPGAs that, on the one hand, generate the digital control signals and receive the digital outputs, and on the other to convert the analog signal coming out of the chip. The analog input of the FPGA has an integrated 14 bit ADC with an LSB of about $200\,{\upmu }\text {V}$. It was used to characterise the pixels using the analog output mode. The FPGAs are programmed with a computer using LABVIEW$^{\copyright }$. For measurements requiring the variation of the input light, a simple led powered with a low noise tunable voltage source was used. The LED was fixed at the end of a dark tube put on top of the imager.

Fig. 7.9

Variance versus signal photon transfer curve (PTC) of the image sensor with a 64 column-level gain and b 1 column-level gain

7.2.2 Conversion Gain Measurement

In order to measure the conversion gain of the readout chain, the photon transfer curve (PTC) measurement technique is used [8]. Figure 7.9a shows the variance versus the signal PTC of the sensor measured from 5000 pixels. It is obtained using the analog output of the sensor and the column-level gain set to 64. The sensor is exposed uniformly to different levels of light provided by the LED and controlled with the voltage source. The variance and mean values are extracted from 100 images for each light level. The PTC curve collapses to zero around 2 V due to the column-level readout chain saturation. The measured overall conversion gain of the readout chain including the pixel, the column-level gain set to 64, the column-level analog buffer and the output analog buffer is measured by estimating the slope in the linear part of the PTC, which leads to $10.5\,\text {m}\text {V}/\text {e}^{-}$. Then, the pixel conversion gain is calculated by dividing the overall conversion gain by the gain of the column-level amplifier and the analog buffers which results in $160\,{\upmu }\text {V}/\text {e}^{-}$. Note that the absolute value of the pixel conversion gain is not used for the input-referred noise measurement. Indeed the output noise RMS measured in mV at the output is directly divided by the overall conversion gain of $10.5\,\text {m}\text {V}/\text {e}^{-}$. Figure 7.9b shows the PTC obtained by performing the same measurement with the column-level gain is set to 1. In this case, the PTC goes to zero around 1.02 V. This time, the saturation originates from the pixel. This curve allows the estimation of the pixel full well capacity. Using the measured conversion gain of $160\,{\upmu }\text {V}/\text {e}^{-}$ the pixel full well capacity is about $6400\,\text {e}^{-}$.

Fig. 7.10

Input-referred temporal read noise histogram of the image sensor with the vertical axis in linear and log scale (inset)

7.2.3 Temporal Read Noise

In order to measure the input-referred noise of the presented imager, the output voltage noise is first measured. Then it is referred to the input using the readout chain conversion gain. This operation was applied to 5000 pixels after performing 100 readouts with a CDS of $5\,{\upmu }\text {s}$ and a line (pixel) readout time of $25\,{\upmu }\text {s}$. The in-pixel SF current bias is set to $1.5\,{\upmu }\text {A}$ and the TX is off. The column-level amplifier gain is set to 64, limiting the bandwidth to about 300 kHz in order to reduce the thermal noise and the noise originating from the next stages. Figure 7.10 shows the resulting histogram of the input-referred TRN. The maximum of the histogram corresponds to $0.48\,\text {e}^-_{\text {rms}}$. The inset of Fig. 7.10 shows the histogram in a log scale highlighting a minority of pixels featuring an RTS noise of a few $\text {e}^-_{\text {rms}}$. The input referred noise of $0.48\,\text {e}^-_{\text {rms}}$ measured at the peak of the noise histogram represents the total noise of the readout chain including the 1 / f and thermal noise. Additionally, the estimation of the input referred 1 / f noise is based on the simulated values of the capacitances connected to the sense node. These values depend on the layout and the process, hence it was expected to obtain values slightly different from the calculation and simulation. Figure 7.11 shows the input referred noise for the two column level gains. It shows a large noise increase in the $\times 1$ gain configuration as the bandwidth becomes much larger (more thermal noise) and all the noise sources after the column-level amplifier are no longer negligible. Thanks to the high column level gain of $\times 64$, the noise originating from the output buffers and analog to digital conversion is completely negligible.

7.2.4 Photo-Response Non-uniformity

This measurement is important in order to verify that the input-referred noise reduction does not come at the cost of higher photo-response non-uniformity (PRNU). The PRNU represents the spatial variation of the gain. It is given as an RMS percentage. For the presented imager, the PRNU was also measured using the PTC. The optical objective of the imager is removed. The chip is exposed directly to the LED put far enough to have a uniform illuminance for all the pixels array. 5000 pixels exposed to the same level of light with the same exposure time are read 100 times. The average output signal is calculated for each of the 5000 pixels. Then the standard deviation of the spatial variation of the pixels output voltage is plotted in Fig. 7.12 as a function of the average over time and space of the pixels output signal for different lighting conditions. The curve is linear as expected and the resulting PRNU corresponds to a value of 0.77%.

Fig. 7.11

Measured input referred noise in the log scale for the two column level gains

Fig. 7.12

PTC alike characterization of the fixed-pattern noise or PRNU. The measured value is 0.77%

Fig. 7.13

Measurement of the dark current as the slope of the output versus exposure time curve

7.2.5 Dark Current

To measure the dark current, the imager is covered protecting it from any light. The chip is set to low column-level gain mode ($\times 1$). The average output signal of the sensor is measured, at room temperature, for different exposure times. Figure 7.13 shows the curve obtained by plotting the measured average output signals of the chip versus the exposure time. For integration times below 300 s, the number of accumulated charges in dark increases linearly with the integration time. The slope factor of the curve indicates a dark current of $5.6\,\text {e}^-/\text {s}$. Usually, integration times above a few tens of ms are not needed. Based on these measurements, the integrated charge originating from the dark current is not supposed to be more than a few $0.05\,\text {e}^-$ which can still be neglected compared to the read noise.

7.2.6 Imager Lag

In order to measure the lag, the imager is exposed to a LED with a constant illumination. The imager exposure time is set to 50 ms. After this integration time, each pixel is read 2 times with a step of $20\,{\upmu }\text {s}$. The signal integrated during $20\,{\upmu }\text {s}$ is considered negligible compared to the signal integrated during 50 ms and represents the floor for the lag assessment. The signal from the second readout of the pixel comes from the electrons left in the PPD after the charge transfer in the first readout. The lag is obtained by dividing the signal from second readout over the one from the first readout. The lag was measured with different input light levels. When the PPD accumulates about 2500 photo-electrons the average measured lag was 0.1%. For an average number of accumulated electrons around 5000 the obtained lag increases to about 1%.

Fig. 7.14

Quantum efficiency of the PPD (active area) obtained by dividing the QE of the sensor by the fill factor of $40\%$

7.2.7 Quantum Efficiency

It is important to verify that the n-well containing the PMOS transistors of the pixel does not act as a photodiode competing with the PPD. To this purpose, a measurement of the quantum efficiency (QE) is required. Figure 7.14 shows the measured QE of the active area of the imager chip. It is obtained by dividing the effective QE by the pixel fill-factor of 40%. The resulting QE is as good as state-of-the-art PPDs designed exclusively using NMOS pixels. This means that the in-pixel n-well does not have a major impact on the PPD collection. Furthermore, the micro-lens layer has not been used in this imager. This layer focuses the light at the active area of the pixels and increases the effective QE.

Fig. 7.15

Images, of the same scene, taken with the presented chip for different amounts of input light. a Shows the obtained image at $0.005 \,\text {lux}$ with a column-level gain set to 64 and an average of 3 photogenerated electrons per pixel. b At $0.066 \,\text {lux}$ with the column-level gain set to 64 and an average of 41 photo-generated electrons per pixel. c At $0.5 \,\text {lux}$ with the column-level gain set to 1 and an average of 320 photo-generated electrons

7.2.8 Imaging Demonstration

Based on the measured performance, the presented imager is supposed to operate in both low light and normal light conditions. In order to validate this idea, images were taken using the presented image sensor in a dark room with a controlled level of light. The imager was set with an exposure time of $12\,\text {ms}$ and a pixel readout time of 25 $\upmu \text {s}$. Figure 7.15a and b show images taken with the chip under different low light levels using the $\times 64$ column gain mode at an average of 3 and 41 photo-generated electrons per pixel, respectively. In Fig. 7.15a, the SNR of the input light (limited by the photon shot noise) is below 5 dB. The dominant noise sources are the photon shot noise and the temporal read noise. One can see that even with such a low input light, the objects in the scene can still be distinguished. In Fig. 7.15b, the SNR of the input light is about 16 dB. Due to the high column gain, one can see that the image is not far from saturation due to voltage swing of the column-level amplifier. In these conditions, the photon shot noise and fixed pattern noise are supposed to be the dominant noise sources. Figure 7.15c shows an image obtained with day-light conditions at an average of 320 photo-generated electrons per pixel and the column-level gain set to 1. Here the input SNR is about 25 dB.

7.3 Discussion and Comparison to State-of-the-Art

The measurement results of the proposed imager, presented in the previous Section, are summarized and compared to recent state-of-the-art works in Table 7.1 showing that the proposed noise reduction technique is efficient. The noise is reduced, as expected, to a record low level of $0.48\,\text {e}^-_{\text {rms}}$ in room temperature which is about 1.5 times lower than state-of-the-art [9, 10] in a full imager with the conventional SF based readout scheme. This record low noise does not come at the cost of a slow readout, a low fill factor or a low SNR. Indeed the line readout time of $25\,{\upmu }\text {s}$ is actually 64 and 5.7 times faster than [9, 10], respectively. A dynamic range of 82.5 dB in the dual gain mode can be achieved.

The improvements achieved in this work were obtained only by making design choices and careful layout based on a detailed noise analysis [1]. The thin oxide transistor used as an SF is a standard “digital” transistor not optimized for analog applications, thus there is still some room left for process optimization at the SF transistor level. Moreover, (4.28) suggests that the input-referred noise can also be mitigated by reducing the contribution of all the parasitic, overlaps and junction capacitances to the sense node ($C_{\text {P}}$). But this approach requires process refinements. Indeed, in [10], the overlap capacitances were reduced by using reset, transfer and gates without low doped drains. In a recently reported work, a mean noise of $0.29\,\text {e}^-_{\text {rms}}$ was measured on a small array of pixels ($12 \times 12$), by using a low doped PN junction isolated from the transfer gate as well as a tapered SF [11]. This result came at the cost of a low full well capacity and a relatively higher lag. In [12], $0.27\,\text {e}^-_{\text {rms}}$ at $-10^{\circ }$C has been reported by implementing a special implant isolating the FD from the TG (reducing the overlap capacitance) and by replacing the reset transistor by an implant connected to a reset clock. But this was achieved at the cost of a high off-chip reset voltage of 25 V and a low full well capacity of $1500\,\text {e}^-$. No characterization has been reported in order to verify the impact of these process modifications on the global performance of the pixels. Note that these process level techniques are compatible with the circuit techniques presented in this work. A combination between the reduction of $C_{\text {P}}$ and using thin oxide SF with optimized gate size is expected to come with even more noise reduction. Indeed, the calculation results presented in Fig. 5.10 show that the input referred noise can be reduced to 0.29 e$^-_{\text {rms}}$ if the capacitance C$_{\text {P}}$ of the sense node is reduced to 0.25 fF, using process refinements [13], instead of the 0.75 fF simulated in the standard process.

Table 7.1 Summary of the imager performance with comparison to state of the art

7.4 Conclusion

This Chapter demonstrates that sub-0.5 electron noise, in a full VGA APS, can be achieved using a standard CIS process by a proper circuit noise optimization exploiting all the degrees of freedom left to the designer for minimizing the total input-referred noise. The proposed techniques include the following steps: (a) introduce enough column level gain to, on one hand, reduce the pixel and column-level amplifier thermal noise and on the other the noise contribution of the next stages, (b) design the column-level amplifier with a minimum number of devices large enough to make the residual noise after auto-zero small enough compared to the SF noise, (c) replace the conventional thick oxide NMOS SF with a minimum width and optimum length thin oxide PMOS, (d) draw a compact layout with common n-well and minimum sense node parasitic capacitance. All these measures result in the majority of the full VGA array pixels peaking at an input-referred TRN of $0.48\,\text {e}^-_{\text {rms}}$ and a minority of pixels showing an RTS noise of a few electrons. The input-referred TRN is measured without CMS and at a short pixel (line) readout time, for a sub-electron read noise CIS, of $25\,{\upmu }\text {s}$.

This work also provides a full characterization of the VGA imager showing that neither of the dynamic range, the imager lag nor the PRNU are compromised with the proposed noise reduction technique. The characterization also shows that the QE of the PPD is not affected by the neighbouring PMOS n-wells.

Note that the proposed approach can be combined with any known additional noise reduction techniques at system (e.g. CMS), device (e.g. buried channel) and process level (e.g. $C_{\text {P}}$ reduction) to further reduce the TRN.