Abstract
We propose a novel adaptive approach capable of handling dynamism of a set of applications on network-on-chip. The applications are subject to throughput or energy consumption constraints. For each application, a set of non-dominated Pareto schedules are computed at design-time in the energy, period and processors space for different cores topologies. Then, upon the starting or ending of an application, a lightweight adaptive run-time scheduler reconfigures the mapping of the live applications according to the available resources, i.e., the available cores of the network-on-chip. This run-time scheduler selects the best topology for each application and maps them to the network-on-chip using the tetris algorithm. This novel scheduling approach is adaptive, it changes the mapping of applications during their execution, and thus delivers just enough power to achieve applications constraints.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Vangal, S.R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, D.F.J., Singh, A., Jacob, T., Jain, S., Erraguntla, V., Roberts, C., Hoskote, Y., Borkar, N., Borkar, S.: An 80-tile sub-100-W Tera-FLOPS processor in 65-nm CMOS. IEEE J. Solid-State Circuits 43(1), 29–41 (2008)
Apple watch battery life: how many hours does it last?. http://www.techradar.com/news/wearables/apple-watch-battery-life-how-many-hours-does-it-last-1291435. Accessed 09 Jan 2015
The battery is dead; long live power management. http://www.design-reuse.com/industryexpertblogs/38079/the-battery-is-dead-long-live-power-management.html. Accessed 09 Jan 2015
Thierry, C., Scherrer, B.: Building controllers for Tetris. Int. Comput. Games Assoc. J. 32(1), 3–11 (2010). http://hal.archives-ouvertes.fr/docs/00/41/89/54/PDF/article.pdf
Karp, R.M.: Reducibility among combinatorial problems. In: Miller, R.E., Thatcher, J.W., Bohlinger, J.D. (eds.) Complexity of Computer Computations. The IBM Research Symposia, pp. 85–103. Springer, Boston (1972). https://doi.org/10.1007/978-1-4684-2001-2_9
Burd, T., Brodersen, R.: Energy efficient CMOS micro-processor design. In: Hawaii International Conference on System Sciences, HICSS 1995, Honolulu (HI), USA. IEEE, Los Alamitos (1995)
Zhu, D., Melhem, R., Mossé, D.: The effects of energy management on reliability in real-time embedded systems. In: International Conference on Computer Aided Design, ICCAD 2004, San Jose (CA), USA, pp. 35–40, November 2004
Elnozahy, E., Kistler, M., Rajamony, R.: Energy-efficient server clusters. In: Workshop on Power-Aware Computing Systems, WPACS 2002, Cambridge (MA), USA, pp. 179–196, February 2002
van Stralen, P., Pimentel, A.: Scenario-based design space exploration of MPSoCs. In: 2010 IEEE International Conference on Computer Design (ICCD), pp. 305–312, October 2010
Stuijk, S., Geilen, M., Basten, T.: A predictable multiprocessor design flow for streaming applications with dynamic behaviour. In: 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), pp. 548–555, September 2010
Murali, S., Coenen, M., Radulescu, A., Goossens, K., De Micheli, G.: A methodology for mapping multiple use-cases onto networks on chips. In: Proceedings of the Conference on Design, Automation and Test in Europe: Proceedings, SER. Date ’06, 3001, pp. 118–123. European Design and Automation Association, Leuven (2006). http://dl.acm.org/citation.cfm?id=1131481.1131519
Yang, B., Guang, L., Xu, T., Yin, A., Santti, T., Plosila, J.: Multi-application multi-step mapping method for many-core network-on-chips. In: NORCHIP 2010, pp. 1–6, November 2010
Schranzhofer, A., Chen, J., Thiele, L.: Dynamic power-aware mapping of applications onto heterogeneous MPSoC platforms. IEEE Trans. Ind. Inform. 6(4), 692–707 (2010). http://dx.doi.org/10.1109/TII.2010.2062192
Huang, J., Raabe, A., Buckl, C., Knoll, A.: A workflow for runtime adaptive task allocation on heterogeneous MPSoCs. In: Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1–6, March 2011
Mariani, G., Avasare, P., Vanmeerbeeck, G., Ykman-Couvreur, C., Palermo, G., Silvano, C., Zaccaria, V.: An industrial design space exploration framework for supporting run-time resource management on multi-core systems. In: Design, Automation Test in Europe Conference Exhibition (DATE), pp. 196–201, March 2010
Singh, A.K., Kumar, A., Srikanthan, T.: Accelerating throughput-aware runtime mapping for heterogeneous MPSOcS. ACM Trans. Des. Autom. Electron. Syst. 18(1), 1–29 (2013). http://doi.acm.org/10.1145/2390191.2390200
Ykman-Couvreur, C., Avasare, P., Mariani, G., Palermo, G., Silvano, C., Zaccaria, V.: Linking run-time resource management of embedded multi-core platforms with automated design-time exploration. IET Comput. Digital Techn. 5(2), 123–135 (2011)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing AG
About this paper
Cite this paper
Assayad, I., Girault, A. (2017). Adaptive Mapping for Multiple Applications on Parallel Architectures. In: Sabir, E., García Armada, A., Ghogho, M., Debbah, M. (eds) Ubiquitous Networking. UNet 2017. Lecture Notes in Computer Science(), vol 10542. Springer, Cham. https://doi.org/10.1007/978-3-319-68179-5_51
Download citation
DOI: https://doi.org/10.1007/978-3-319-68179-5_51
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-68178-8
Online ISBN: 978-3-319-68179-5
eBook Packages: Computer ScienceComputer Science (R0)