Abstract
An application program can go through significant optimizing and parallelizing transformations, both automated and human guided, before being mapped to an architecture. Formal verification of these transformations is crucial to ensure that they preserve the original behavioural specification. PRES+ model (Petri net based Representation of Embedded Systems) encompassing data processing is used to model parallel behaviours more vividly. This paper presents a translation validation tool for verifying optimizing and parallelizing code transformations by checking equivalence between two PRES+ models, one representing the source code and the other representing its optimized and (or) parallelized version.
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S. Bandyopadhyay is now working at HPI, Potsdam, Germany, email: soumyadip.bandyopadhyay@hpi.de
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Acknowledgment
Santonu Sarkar has been partially supported by Science and Engineering Research Board, Govt. of India project (SB/S3/EECE/0170/2014) for this research work.
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Bandyopadhyay, S., Sarkar, S., Sarkar, D., Mandal, C. (2017). SamaTulyata: An Efficient Path Based Equivalence Checking Tool. In: D'Souza, D., Narayan Kumar, K. (eds) Automated Technology for Verification and Analysis. ATVA 2017. Lecture Notes in Computer Science(), vol 10482. Springer, Cham. https://doi.org/10.1007/978-3-319-68167-2_8
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DOI: https://doi.org/10.1007/978-3-319-68167-2_8
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