High Frame Rate Real-Time Scene Change Detection System
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Scene change detection, one of the fundamental and most important problem of computer vision, plays a very important role in the realization of a complete industrial vision system as well as automated video surveillance system - for automatic scene analysis, monitoring, and generation of alerts based on relevant changes in a video stream. Therefore, in addition to being accurate and robust, a successful scene change detection system must also be of very high frame rate in order to detect scene changes which goes off within a glimpse of the eye and often goes unnoticeable by the conventional frame rate cameras. Keeping the high frame rate processing as main focus, a very high frame rate real-time scene change detection system is developed by leveraging VLSI design to achieve high performance. This is accomplished by proposing, designing, and implementing an area-efficient scene change detection VLSI architecture on FPGA-based IDP Express platform. The developed prototype of complete real-time scene change detection system is capable of processing 2000 frames per second for 512 × 512 video resolution and is tested for live incoming video streams from high speed camera. The proposed and implemented system architecture is adaptable and scalable for different video resolutions and frame rates.
KeywordsHigh speed scene change detection VLSI architecture FPGA implementation Automated video surveillance system
Sanjay Singh is thankful to Prof. Raj Singh, Chief Scientist and Group Leader, IC Design Group, CSIR-CEERI, Pilani and Dr. A.S. Mandal, Chief Scientist, CSIR-CEERI, Pilani for their constant support and motivation. The financial support of Ministry of Electronics & Information Technology (MeitY), Govt. of India is gratefully acknowledged.
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