Bridging the Gap Between Evolvable Hardware and Industry Using Cartesian Genetic Programming

Part of the Emergence, Complexity and Computation book series (ECC, volume 28)


Advancements in technology developed in the early nineties have enabled researchers to successfully apply techniques of evolutionary computation in various problem domains. As a consequence, a new research direction referred to as evolvable hardware (EHW) focusing on the use of evolutionary algorithms to create specialized electronics has emerged. One of the goals of the early pioneers of EHW was to evolve complex circuits and overcome the limits of traditional design. Unfortunately, evolvable hardware found itself in a critical stage around 2010 and a very pessimistic future for EHW-based digital circuit synthesis was predicted. The problems solved by the community were of the size and complexity of that achievable in fifteens years ago and seldom compete with traditional designs. The scalability problem has been identified as one of the most difficult problems that researchers are faced with and it was not clear whether there existed a path forward that would allow the field to progress. Despite that, researchers have continued to investigate how to overcome the scalability issues and significant progress has been made in the area of evolutionary synthesis of digital circuits in recent years. The goal of this chapter is to summarize the progress in the evolutionary synthesis of gate-level digital circuits, and to identify the challenges that need to be addressed to enable evolutionary methods to penetrate into industrial practice.



This work was supported by The Ministry of Education, Youth and Sports of the Czech Republic from the National Programme of Sustainability (NPU II); project IT4Innovations excellence in science - LQ1602.


  1. 1.
    Albrecht, C.: IWLS 2005 benchmarks. Technical Report, published at 2005 International Workshop on Logic Synthesis (June 2005)Google Scholar
  2. 2.
    Amaru, L., Gaillardon, P.-E., De Micheli, G.: The EPFL combinational benchmark suite. In: 24th International Workshop on Logic & Synthesis (2015)Google Scholar
  3. 3.
    Brglez, F., Fujiwara, H.: A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran. In: Proceedings of IEEE International Symposium Circuits and Systems (ISCAS 85), pp. 677–692. IEEE Press, Piscataway, N.J. (1985)Google Scholar
  4. 4.
    Coello, C.A.C., Christiansen, A.D., Aguirre, A.H.: Automated design of combinational logic circuits by genetic algorithms. In: Artificial Neural Nets and Genetic Algorithms: Proceedings of the International Conference in Norwich, U.K., 1997, pp. 333–336. Springer, Vienna (1998). doi: 10.1007/978-3-7091-6492-1_73. ISBN 978-3-7091-6492-1
  5. 5.
    Goldman, B.W., Punch, W.F.: Analysis of Cartesian genetic programming’s evolutionary mechanisms. IEEE Trans. Evol. Comput. 19(3):359–373 (2015). doi: 10.1109/TEVC.2014.2324539. ISSN 1089-778X
  6. 6.
    Gordon, T.G.W., Bentley, P.J.: On evolvable hardware. In: Soft Computing in Industrial Electronics, pp. 279–323. Physica-Verlag, London, UK (2002)Google Scholar
  7. 7.
    Greenwood, G.W., Tyrrell. A.M.: Introduction to evolvable hardware: a practical guide for designing self-adaptive systems. In: IEEE Press Series on Computational Intelligence. Wiley-IEEE Press (2006). ISBN 0471719773Google Scholar
  8. 8.
    Haddow, P.C., Tyrrell, A.: Challenges of evolvable hardware: past, present and the path to a promising future. Genet. Progr. Evol. Mach. 12, 183–215 (2011)CrossRefGoogle Scholar
  9. 9.
    Haddow, P.C., Tufte, G., van Remortel, P.: Shrinking the genotype: L-systems for EHW? In: Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware. LNCS, vol. 2210, pp. 128–139. Springer (2001)Google Scholar
  10. 10.
    Hassoun, S., Sasao, T. (eds.): Logic Synthesis and Verification. Kluwer Academic Publishers, Norwell, MA, USA (2002)Google Scholar
  11. 11.
    Higuchi, T., Niwa, T., Tanaka, T., Iba, H., de Garis, H., Furuya, T.: Evolving hardware with genetic learning: a first step towards building a Darwin machine. In: Proceedings of the 2nd International Conference on Simulated Adaptive Behaviour, pp. 417–424. MIT Press (1993)Google Scholar
  12. 12.
    Higuchi, T., Liu, Y., Yao, X. (eds.): Evolvable Hardware. Springer Science+Media LLC, New York (2006)MATHGoogle Scholar
  13. 13.
    Hrbacek, R., Sekanina, L.: Towards highly optimized Cartesian genetic programming: from sequential via SIMD and thread to massive parallel implementation. In: Proceedings of 2014 Annual Conference on Genetic and Evolutionary Computation, pp. 1015–1022. ACM, New York, NY, USA (2014). doi: 10.1145/2576768.2598343
  14. 14.
    Imamura, K., Foster, J.A., Krings, A.W.: The test vector problem and limitations to evolving digital circuits. In: Proceedings of the 2nd NASA/DoD Workshop on Evolvable Hardware, pp. 75–79. IEEE Computer Society Press (2000)Google Scholar
  15. 15.
    Koza, J.R.: Genetic Programming: On the Programming of Computers by Means of Natural Selection. MIT Press, Cambridge, MA (1992)MATHGoogle Scholar
  16. 16.
    Koza, J.R.: Human-competitive results produced by genetic programming. Genet. Progr. Evol. Mach. 11(3–4), 251–284 (2010)CrossRefGoogle Scholar
  17. 17.
    McElvain, K.: LGSynth93 benchmark set version 4.0 (1993)Google Scholar
  18. 18.
    Miller, J.F.: Digital filter design at gate-level using evolutionary algorithms. In: Proceedings of the Genetic and Evolutionary Computation Conference, GECCO 1999, pp. 1127–1134. Morgan Kaufmann (1999a)Google Scholar
  19. 19.
    Miller, J.F.: An empirical study of the efficiency of learning Boolean functions using a Cartesian Genetic Programming approach. In Banzhaf, W., Daida, J., Eiben, A.E., Garzon, M.H., Honavar, V., Jakiela, M., Smith, R.E. (Eds), Proceedings of the Genetic and Evolutionary Computation Conference, vol. 2, pp. 1135–1142. Morgan Kaufmann, Orlando, Florida, USA. 13–17 July (1999b). ISBN 1-55860-611-4Google Scholar
  20. 20.
    Miller, J.F.: Cartesian Genetic Programming, Springer (2011)Google Scholar
  21. 21.
    Miller, J.F., Thomson, P.: Cartesian genetic programming. In: Proceedings of the 3rd European Conference on Genetic Programming EuroGP2000. LNCS, vol. 1802, pp. 121–132. Springer (2000)Google Scholar
  22. 22.
    Miller, J.F., Thomson, P., Fogarty, T.: Designing electronic circuits using evolutionary algorithms. arithmetic circuits: a case study. In: Genetic Algorithms and Evolution Strategies in Engineering and Computer Science, pp. 105–131. Wiley (1997)Google Scholar
  23. 23.
    Miller, J.F., Job, D., Vassilev, V.K.: Principles in the evolutionary design of digital circuits—part I. Genet. Progr. Evol. Mach. 1(1), 8–35 (2000)MATHGoogle Scholar
  24. 24.
    Miller, J.F., Harding, S.L., Tufte, G.: Evolution-in-materio: evolving computation in materials. Evol. Intell. 7(1):49–67 (2014). doi: 10.1007/s12065-014-0106-6. ISSN 1864-5917
  25. 25.
    Sekanina, L.: Evolvable components: from theory to hardware implementations. In: Natural Computing Series. Springer (2004)Google Scholar
  26. 26.
    Sekanina, L., Vasicek, Z.: Evolutionary computing in approximate circuit design and optimization. In: 1st Workshop on Approximate Computing (WAPCO 2015), pp. 1–6 (2015)Google Scholar
  27. 27.
    Shanthi, A.P., Parthasarathi, R.: Practical and scalable evolution of digital circuits. Appl. Soft Comput. 9(2), 618–624 (2009)CrossRefGoogle Scholar
  28. 28.
    Stoica, A., Keymeulen, D., Tawel, R., Salazar-Lazaro, C., Li, W.-T.: Evolutionary experiments with a fine-grained reconfigurable architecture for analog and digital CMOS circuits. In: Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware, EH 1999, pp. 76–84. IEEE Computer Society, Washington, DC, USA (1999)Google Scholar
  29. 29.
    Stomeo, E., Kalganova, T., Lambert, C.: Generalized disjunction decomposition for evolvable hardware. IEEE Trans. Syst. Man Cybern. Part B 36(5), 1024–1043 (2006)CrossRefGoogle Scholar
  30. 30.
    Thompson, A.: Silicon evolution. In: Proceedings of the First Annual Conference on Genetic Programming, GECCO ’96, pp. 444–452. MIT Press, Cambridge, MA, USA (1996)Google Scholar
  31. 31.
    Trefzer, M.A., Tyrrell, A.M.: Evolvable Hardware: From Practice to Application. Springer, Berlin, Heidelberg (2015)CrossRefGoogle Scholar
  32. 32.
    Turner, A.J., Miller, J.F.: Neutral genetic drift: an investigation using Cartesian genetic programming. Genet. Progr. Evol. Mach. 16(4):531–558 (2015). doi: 10.1007/s10710-015-9244-6. ISSN 1573-7632
  33. 33.
    Vasicek, Z.: Cartesian GP in optimization of combinational circuits with hundreds of inputs and thousands of gates. In: Proceedings of the 18th European Conference on Genetic Programming—EuroGP. LCNS 9025, pp. 139–150. Springer International Publishing (2015)Google Scholar
  34. 34.
    Vasicek, Z., Sekanina, L.: Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genet. Progr. Evol. Mach. 12(3), 305–327 (2011)CrossRefGoogle Scholar
  35. 35.
    Vasicek, Z., Sekanina, L.: How to evolve complex combinational circuits from scratch? In: Proceedings of the 2014 IEEE International Conference on Evolvable Systems, pp. 133–140. IEEE (2014)Google Scholar
  36. 36.
    Vasicek, Z., Slany, K.: Efficient phenotype evaluation in Cartesian genetic programming. In: Proceedings of the 15th European Conference on Genetic Programming. LNCS 7244, pp. 266–278. Springer (2012)Google Scholar
  37. 37.
    Vasicek, Z., Bidlo, M., Sekanina, L.: Evolution of efficient real-time non-linear image filters for fpgas. Soft Comput. 17(11):2163–2180 (2013). doi: 10.1007/s00500-013-1040-8. ISSN 1433-7479
  38. 38.
    Vassilev, V., Job, D., Miller, J.F.: Towards the automatic design of more efficient digital circuits. In: Lohn, J., Stoica, A., Keymeulen, D., Colombano, S. (eds.) Proceedings of the 2nd NASA/DoD Workshop on Evolvable Hardware, pp. 151–160. IEEE Computer Society, Los Alamitos, CA, USA (2000)Google Scholar
  39. 39.
    Vassilev, V.K., Miller, J.F., Fogarty, T.C.: Digital circuit evolution and fitness landscapes. In: Proceedings of the Congress on Evolutionary Computation, vol. 2. IEEE Press, 6-9 July (1999)Google Scholar
  40. 40.
    Zhao, S., Jiao, L.: Multi-objective evolutionary design and knowledge discovery of logic circuits based on an adaptive genetic algorithm. Genet. Progr. Evol. Mach. 7(3), 195–210 (2006)Google Scholar

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© Springer International Publishing AG 2018

Authors and Affiliations

  1. 1.Faculty of Information Technology, Centre of Excellence IT4InnovationsBrno University of TechnologyBrnoCzech Republic

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