Implementing a Per-Flow Token Bucket Using Open Packet Processor

  • Giuseppe Bianchi
  • Marco Bonola
  • Valerio Bruschi
  • Luca Petrucci
  • Salvatore PontarelliEmail author
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 766)


In this paper we show how to realize a per-flow QoS (Quality of Service) policy based on the token bucket algorithm using OPP (Open Packet Processor), a recently proposed stateful programmable dataplane. OPP is configured as a switch that enforce a token bucket policy independently on each flow processed by the switch controlling their bandwidth and burstiness. The paper shows the design of the token bucket algorithm using the extended finite state machine (EFSM) abstraction provided by OPP and discusses the details of the implementation carried out using a proof-of-concept FPGA prototype of the OPP pipeline.



This work is partially supported by the EU Commission in the frame of the Horizon 2020 projects BEBA (grant #644122) and SUPERFLUIDITY (grant #671566).


  1. 1.
    Bosshart, P., Gibb, G., Kim, H.S., Varghese, G., McKeown, N., Izzard, M., Mujica, F., Horowitz, M.: Forwarding metamorphosis: fast programmable match-action processing in hardware for SDN. In: Proceedings of the Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications (SIGCOMM) (2013)Google Scholar
  2. 2.
    Intel Ethernet Switch FM5000/FM6000 Datasheet. Accessed 16 May 2017
  3. 3.
    XPliant Ethernet Switch Product Family. Accessed 16 May 2017
  4. 4.
    Sivaraman, A., et al.: Packet transactions: high-level programming for line-rate switches. In: Proceedings of the 2016 Conference on ACM SIGCOMM 2016 Conference. ACM (2016)Google Scholar
  5. 5.
    The language consortium: P416 Language SpecificationGoogle Scholar
  6. 6.
    Moshref, M., et al.: Flow-level state transition as a new switch primitive for SDN. In: Proceedings of the Third Workshop on Hot Topics in Software Defined Networking. ACM (2014)Google Scholar
  7. 7.
    Bianchi, G., Bonola, M., Capone, A., Cascone, C.: OpenState: programming platform-independent stateful openflow applications inside the switch. ACM SIGCOMM Comput. Commun. Rev. 44(2), 44–51 (2014)CrossRefGoogle Scholar
  8. 8.
    Bianchi, G., et al.: Open Packet Processor: a programmable architecture for wire speed platform-independent stateful in-network processing.
  9. 9.
    Gibb, G., Varghese, G., Horowitz, M., McKeown, N.: Design principles for packet parsers. In: ACM/IEEE Architectures for Networking and Communications Systems, p. 13Google Scholar
  10. 10.
    Song, H.: Protocol-oblivious forwarding: Unleash the power of SDN through a future-proof forwarding plane. In: Proceedings of the Second ACM SIGCOMM Workshop on Hot Topics in Software Defined Networking (HotSDN 2013), pp. 127–132. ACM (2013)Google Scholar
  11. 11.
    Pontarelli, S., Bonola, M., Bianchi, G., Capone, A., Cascone, C.: Stateful openflow: hardware proof of concept. In: IEEE 16th International Conference on High Performance Switching and Routing (HPSR) (2015)Google Scholar
  12. 12.
    Bianchi, G., Bonola, M., Pontarelli, S.: On the feasibility of “breadcrumb” trails within OpenFlow switches. In: IEEE European Conference on Networks and Communications (EuCNC) (2016)Google Scholar
  13. 13.
    Zilberman, N., Audzevich, Y., Covington, G., Moore, A.W.: NetFPGA SUME: toward 100 Gbps as research commodity. IEEE Micro 34(5), 32–41 (2014)CrossRefGoogle Scholar
  14. 14.
    Virtex-7 Family Overview. Accessed 16 May 2017
  15. 15.
    Brelet, J.-L.: Using block RAM for high performance read/write TCAMs. Xilinx XAPP204 (2012)Google Scholar
  16. 16.
    Ullah, Z., Jaiswal, M.K., Chan, Y.C., Cheung, R.C.C.: FPGA Implementation of SRAM-based ternary content addressable memory. In: IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW) (2012)Google Scholar
  17. 17.
    Jiang, W.: Scalable ternary content addressable memory implementation using FPGAs. In: Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS) (2013)Google Scholar

Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  • Giuseppe Bianchi
    • 1
  • Marco Bonola
    • 1
  • Valerio Bruschi
    • 1
  • Luca Petrucci
    • 1
  • Salvatore Pontarelli
    • 1
    Email author
  1. 1.CNITUniversitá di Roma Tor VergataRomeItaly

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