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Compiling Depth-Optimized Circuits for Multi-Round MPC Protocols

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Compilation for Secure Multi-party Computation

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Abstract

Many MPC protocols, such as GMW and SPDZ, have a round complexity that is dependent on the circuit’s depth. When deploying these protocols in real world network settings, with network latencies in the range of tens or hundreds of milliseconds, the round complexity quickly becomes a significant performance bottleneck. In this chapter, we describe compiler extension to CBMC-GC (This chapter is based on our paper “Compiling Low Depth Circuits for Practical Secure Computation” (Büscher et al. ESORICS 2016: 21st European Symposium on Research in Computer Security, Part II. Springer, Heidelberg, 2016).) that optimizes circuits for a minimal depth. We first introduce novel optimized building blocks that are up to 50% shallower than previous constructions. Second, we present multiple high- and low-level depth-minimization techniques. Our implementation achieves significant depth reductions over hand-optimized circuits (for some applications up to 2.5). Moreover, evaluating exemplary functionalities in the GMW protocol, we show that depth reductions lead to significant speed-ups in real-world network setting.

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Notes

  1. 1.

    Even though, MPC is often benchmarked in a LAN setting, a WAN setting is the more natural deployment model of MPC.

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Büscher, N., Katzenbeisser, S. (2017). Compiling Depth-Optimized Circuits for Multi-Round MPC Protocols. In: Compilation for Secure Multi-party Computation. SpringerBriefs in Computer Science. Springer, Cham. https://doi.org/10.1007/978-3-319-67522-0_6

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