Abstract
This chapter considers functional decompositions of index generation functions. A Monte Carlo method to predict column multiplicities of the decomposition charts is presented. With this, we can efficiently find a circuit structure to implement the function. Our goal is not to find a minimum column multiplicity of a given function, but to predict the column multiplicities of random index generation functions. With these results, we can estimate the size of the programmable architecture when we know only the number of inputs and registered vectors.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsNotes
- 1.
For simplicity, readers can assume that LUTs are used to implement the functions.
- 2.
This assumes that k ≤ 2n−s.
References
R.L. Ashenhurst, The decomposition of switching functions, in International Symposium on the Theory of Switching, April 1957, pp. 74–116
V. Bertacco, M. Damiani, The disjunctive decomposition of logic functions, in IEEE/ACM International Conference on Computer-Aided Design (ICCAD-1997), November 1997, pp. 78–82
R.K. Brayton, G.D. Hachtel, C.T. McMullen, A.L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis (Kluwer Academic, Boston, 1984)
H.A. Curtis, A New Approach to the Design of Switching Circuits (D. Van Nostrand Co., Princeton, NJ, 1962)
V. Kravets, K. Sakallah, Constructive library-aware synthesis using symmetries, in Design, Automation and Test in Europe (DATE-2000), Paris, March 2000, pp. 208–213
Y-T. Lai, M. Pedram, S.B.K. Vrudhula, BDD based decomposition of logic functions with application to FPGA synthesis, in 30th ACM/IEEE Design Automation Conference (DAC-1993), June 1993, pp. 642–647
C.L. Liu, Introduction to Combinatorial Mathematics (McGraw-Hill, New York, 1968)
Y. Matsunaga, An exact and efficient algorithm for disjunctive decomposition, in Synthesis and System Integration of Mixed Technologies (SASIMI-1998), October 1998, pp. 44–50
H. Nakahara, T. Sasao, M. Matsuura, H. Iwamoto, Y. Terao, A memory-based IPv6 lookup architecture using parallel index generation units. IEICE Trans. Inf. Syst. E98-D(2), 262–271 (2015)
T. Sasao, FPGA design by generalized functional decomposition, in Logic Synthesis and Optimization, ed. by T. Sasao (Kluwer Academic, Dordrecht, 1993), pp. 233–258
T. Sasao, Switching Theory for Logic Synthesis (Kluwer Academic, Dordrecht, 1999)
T. Sasao, Totally undecomposable functions: applications to efficient multiple-valued decompositions, in International Symposium on Multiple-Valued Logic (ISMVL-1999), Freiburg, 20–23 May 1999, pp. 59–65
T. Sasao, Memory-Based Logic Synthesis (Springer, New York, 2011)
T. Sasao, Index generation functions: tutorial. J. Mult. Valued Log. Soft Comput. 23(3–4), 235–263 (2014)
T. Sasao, A realization of index generation functions using multiple IGUs, in International Symposium on Multiple-Valued Logic (ISMVL-2016), Sapporo, 17–19 May 2016, pp.113–118
T. Sasao, K. Matsuura, Y. Iguchi, A heuristic decomposition of index generation functions with many variables, in The 20th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI-2016), Kyoto, 24 October 2016, R1–6, pp. 23–28
T. Sasao, K. Matsuura, Y. Iguchi, An algorithm to find optimum support-reducing decompositions for index generation functions, in Design, Automation and Test in Europe (DATE-2017), Lausanne, 27–31 March 2017
Acknowledgements
This research is partly supported by the Japan Society for the Promotion of Science (JSPS) Grant in Aid for Scientific Research. Discussion with Mr. Kyu Matsuura was useful to improve Sect. 5. Also, the reviewers’ comments improved the presentation of the chapter.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG
About this chapter
Cite this chapter
Sasao, T., Butler, J.T. (2018). Decomposition of Index Generation Functions Using a Monte Carlo Method. In: Reis, A., Drechsler, R. (eds) Advanced Logic Synthesis. Springer, Cham. https://doi.org/10.1007/978-3-319-67295-3_10
Download citation
DOI: https://doi.org/10.1007/978-3-319-67295-3_10
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-67294-6
Online ISBN: 978-3-319-67295-3
eBook Packages: EngineeringEngineering (R0)