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High-Throughput Hardware Architecture for LDPC Decoders

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Application-Specific Hardware Architecture Design with VHDL

Part of the book series: Signals and Communication Technology ((SCT))

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Abstract

The error probability considering communication channel such as electromagnetic wave through space is high. This is why channel encoding for error correction is commonly used. Powerful error correction codes are available (i.e., low-density parity check codes LDPC), unfortunately, the more powerful the codes are, the more computational cost for the decoding at destination increases. Nevertheless, high performance computing architectures (e.g., graphic processing units, FPGAs) are available for implementing high-throughput decoders. This chapter focuses on the implementation of high-throughput LDPC decoders using field programmable gate array (FPGA) technology.

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Authors and Affiliations

  1. National Institute for Research and Development of Isotopic and Molecular Technologies, Cluj-Napoca, Romania

    Bogdan Belean

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  1. Bogdan Belean
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Belean, B. (2018). High-Throughput Hardware Architecture for LDPC Decoders. In: Application-Specific Hardware Architecture Design with VHDL. Signals and Communication Technology. Springer, Cham. https://doi.org/10.1007/978-3-319-65025-8_3

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  • DOI: https://doi.org/10.1007/978-3-319-65025-8_3

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-65023-4

  • Online ISBN: 978-3-319-65025-8

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