Abstract
Cryptographic applications like symmetric encryption algorithms can be implemented either in bit-slice or word-parallel fashion. The conversion between the two data representations corresponds to transposing a bit-matrix with variables as row vectors. In previous work we have demonstrated that combining the best of both variants, i.e. executing part of the code in bit-slice, and part of the code in word-parallel manner, can improve performance considerably, but most of the advantage is spent for the conversion. Here, we examine the conversion routine closer and deviate different levels of hardware and software support that can accelerate the conversion, ranging from existing but seldom used instructions to completely new instructions that might be implemented in future systems. We quantify the acceleration achieved by each level of support, and provide preliminary experimental results.
Keywords
- Bit matrix transposition
- Bit shuffle instructions
- High-speed encryption
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Eitschberger, P., Keller, J., Holmbacka, S. (2017). Hardware and Software Support for Transposition of Bit Matrices in High-Speed Encryption. In: Yan, Z., Molva, R., Mazurczyk, W., Kantola, R. (eds) Network and System Security. NSS 2017. Lecture Notes in Computer Science(), vol 10394. Springer, Cham. https://doi.org/10.1007/978-3-319-64701-2_12
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DOI: https://doi.org/10.1007/978-3-319-64701-2_12
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