Abstract
This chapter introduces the basic silicon properties and their technical application to set the scene and provide understanding of the silicon sensors functionality. The writing concentrates on examples of detectors used in particle physics experiments – in the High Energy Physics HEP. It also describes the working principle of silicon sensors as particle detectors, together with an explanation of their production processes and design parameter considerations.
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Notes
- 1.
Concept of “holes”: if an electron absorbs \(E \ge \varDelta E_{g}\) (\(E_{Gap}\)) it can enter the conduction band leaving a vacancy called “hole” representing a positive charge in the valence band which can move in an applied electric field. These holes are treated like particles and follow the Fermi–Dirac statistic.
- 2.
Fermi energy: “the highest possible energy of a fermion at \(T =0\) K”.
- 3.
Not to compare with low resistivity IC silicon material with 10 – 100 \(\Omega \)cm.
- 4.
The lowest conduction band energy does not lie at the same position in k-space as the highest valence band energy.
- 5.
The capture rate is similar, but here also the concentration of free electrons (holes) in the conduction (valence) band to “feed” them are relevant.
- 6.
According to the principle of detailed balance the concentrations of free electrons in the conduction band and free holes in the valence band have to be constant.
- 7.
Depleted of free charge carriers.
- 8.
Assuming an “abrupt” change of \(\varrho (x)\) (see Fig. 1.5d – full line).
- 9.
Device measuring L inductance, C capacitance and R resistance.
- 10.
(1) DEPEFTs are silicon sensors with intrinsic amplification, they are introduced in Sect. 1.12.6. (2) There are also photo-avalanche diodes and silicon photo-multiplier SiPM with intrinsic charge amplification, but these are not used as segmented sensors for high energy tracking sensors. (3) LGADs, a recent development, are similar to SiPM and introduced in Sect. 1.12.8.
- 11.
In the most common sensor p-in-n, holes are collected at the segmented side, but for n-in-p, n-in-n or double-sided sensors electrons are also collected.
- 12.
In an n-in-n, n-in-p or a double-sided detector, electrons drift to the \(n^+\) doped strips.
- 13.
Often, highest doping concentration in the backplane, here \(n^{++}\), lower doping for the strips/pixel, here \(p^+\) and lowest doping for the bulk, here n to achieve high resistivity in the bulk and low resistivity elsewhere. The extra high doping for the backplane is not done at every vendor.
- 14.
For a simpler figure we avoid the use of \(^{+++}\) and write \(p^+\) for \(p^+\)-stop although its doping concentration is lower then for the \(n^+\) strip.
- 15.
Most often by ultrasonic wire-bonding.
- 16.
Another example would be a cylindrical drift tube.
- 17.
Assuming a uniform charge distribution, a track crossing between two strips at \(\frac{3}{4} \cdot pitch\) will store \(\frac{1}{4} \cdot charge\) on the left strip and \(\frac{3}{4} \cdot charge \) on the right strip.
- 18.
Approximately a Gaussian distribution, due to the diffusion profile.
- 19.
With the correct potential, electric field lines end here; otherwise they would adjust their potential and not collect any charge.
- 20.
\(\sigma _ x \approx \) \(p/\sqrt{12}\) arising from geometrical reflections: \(<\!\varDelta x^{2}>= \frac{1}{p}\int ^{p/2}_{-p/2}x^{2}dx =\frac{p^2}{12}\).
- 21.
Reminder, the \(p^+\)-stops are negatively charged/have a negative space charge.
- 22.
Common strip orientations are \(90^{\circ }\) or a small stereo angle like 0.1 – \(2^{\circ }\).
- 23.
Polyimide (sometimes abbreviated PI) is a polymer of imide monomers, it is resilient against ionising radiation.
- 24.
Phosphorous for n-bulk sensors; boron for p-bulk sensors.
- 25.
The reason to dope the vertical cut edges is to define a well known doping profile and potential, dominating any crystal defect from the cutting.
- 26.
FAB fabrication line of silicon devices, CMS sensors, etc.
- 27.
Negative charged passivation for p-type, e.g. Al\(_2\)O\(_3\) and positive charged for n-type, e.g. SiO\(_2\) or Si\(_3\)N\(_4\).
- 28.
Often split bias is used, where both coupling oxides carry \(V_\mathrm{bias}/2\) or the chip is kept floating.
- 29.
At least for p-in-n sensors, where the field builds up from the junction side.
- 30.
Without full bias voltage, only the capacitance to the plane of the SCR would be measured.
- 31.
Known as a “pinhole” (see Sect. 1.6.3).
- 32.
Thermal noise.
- 33.
A square is a defined square size to allow normalization of a resistance per area.
- 34.
Strong dependence on the ASIC design.
- 35.
A quasi-static capacitance measurement, where \(Q =CV \) is measured for several values of V, works only with negligible current. In the case of a pinhole, the applied voltage V initiates a current driving the measurement value into overflow – pinhole signature.
- 36.
The SVX4, the successor of the CDF SVX3 chip.
- 37.
Reminder: Majority carriers for n-type bulk: electrons, for p-type bulk: holes.
- 38.
In a graphic way one can say the additional space charge of the filled traps decreases/increases the depletion zone thus the full capacitance.
- 39.
Arrhenius plot: Plot the exponential temperature dependent decay \(e^{-\frac{E_A}{k_B T}}\) in logarithmic scaling against the inverse temperature.
- 40.
If cooled at zero bias voltage the majority carrier traps are already being filled during the process. In case of a very high majority trap level concentration with respect to the majority carriers itself, only the traps near midgap are being filled.
- 41.
For practical reasons with a constant heat rate time can also be substituted with temperature \(T=T_0+\beta (t)\).
- 42.
The relation is correct for a fully depleted diode otherwise D becomes w, the thickness of the depletion zone.
- 43.
The induced signal ends so fast that is gets filtered by the bandwidth of the amplifier and/or scope (several GHz). In simulation, however, one sees the very fast and short amplitude.
- 44.
The jargon is to ‘inject’ electrons or to ‘inject’ holes.
- 45.
Again, this is jargon for generation of electron-holes with laser light, while one charge carrier sort is collected immediately at the near electrode, here electrons thus holes are ‘injected’.
- 46.
This is true for short current integration times as necessary for the LHC (bunch-crossings every 25 ns); with integration times longer than de-trapping times, the full charge would be measured.
- 47.
If \(1/\tau _{tr}>1/\tau _{eff _{e, h}}\), \(Q_C\) would be too high or vice versa \(1/\tau _{tr}<1/\tau _{eff _{e, h}}\) too low.
- 48.
Any wavelength above 1150 nm would do the trick; the absorption maximum is at about \(\lambda \)= 1300 nm. \(\lambda \)= 1500 nm lasers are commercially available from telecommunication industry.
- 49.
Typical pulses are 100 fs wide.
- 50.
1-ppba: part per billion active (impurities).
- 51.
1955, early silicon ingots if 3/4 to 1 in. diameter were fabricated by Montecatini.
- 52.
To process a double-sided sensor, the wafer needs to be polished on both sides. This step, as easy as it sounds, is not available on both sides from all manufacturers.
- 53.
The mask itself must be very precise and is very expensive.
- 54.
LHCb is one of the four detectors at the LHC, the sensors for the VErtex LOcator VELO detector are shaped roughly as a half-moon and the round cutting was achieved by laser cutting.
- 55.
Recently 200 \(\upmu \)m on an 8 in. wafer.
- 56.
Double correlated sampling: Charge is integrated on a capacitor \(C_1\) with signal absent, while the charge of the next time slot is stored in capacitor \(C_2\) with potentially signal present. The charge difference between both capacitors represents the SIGNAL. This technique reduces leakage current effects and low frequency noise.
- 57.
Very Large Scale Integration VLSI stands for the process of creating Integrated Circuits ICs by combining thousands of transistor-based circuits into a single chip.
- 58.
In the first version, with DC coupling, even quadruple correlated sampling was used to suppress the direct current flowing into the amplifier.
- 59.
Initially, these parts were even produced separately, only later a monolithic chip was produced.
- 60.
It was designed for the planned RUNIIb of the TEVATRON, which was finally abandoned.
- 61.
Common mode: Baseline fluctuations common for all channels of a chip.
- 62.
The chip allows to offset the centre of the acceptance window to accommodate for tracks with an angle depending on the 3D location of the module in the Tracker.
- 63.
Early prototyping is done together with the future pixel chip from RD53 (see later) to save engineering cost.
- 64.
Often also called flip-chip.
- 65.
A previous version had a bump of 150 \(\upmu \)m which was finally decreased to reduce the capacitive load.
- 66.
The shunt-LDO regulator is a new regulator concept which combines a shunt and a Low Drop-Out LDO regulator, it is also implemented in the ATLAS FE-I4A ASIC [119].
- 67.
Maybe 4 by 4.
- 68.
or PMOS in n-bulk devices. Today, there are also more complicated designs/processes with “nested wells”/tripple well technology, allowing both NMOS and PMOS.
- 69.
EPI layer: Created through epitaxy or epitaxial growth: A thin (0.5 – 20 \(\upmu \)m) layer of single crystal silicon is grown over a single crystal base substrate through chemical vapour deposition CVD. For HEP sensors thickness up to 60 \(\upmu \)m are processed. These devices are different to the ingot growth and laser cutting described in Sect. 1.9.1.
- 70.
Generally, the term SOI describes the basic wafer type “silicon chemically bonded to insulator to silicon” which is being used in other processes as well, e.g. use one silicon face as handle wafer. Thus, there is a potential mix-up with the term. Today 2017, SOI sensors are in the HV-CMOS family, see next section.
- 71.
Voltage to fully deplete the sensor.
- 72.
The bonding of the two wafers is done at the SOI wafer producer.
- 73.
To limit the pixel capacitance, designs exists that split-up the deep N-well into several connected blocks.
- 74.
The glue has to be very thin, in the order of ten micrometers only, to achieve a good coupling.
- 75.
Threshold values well below 1000 electrons have been achieved.
- 76.
Defined by the field of view of the lithographic equipment; normally featuring one or more individual electronic chips.
- 77.
The ‘rolling shutter’ concept as used in the ALICE upgrade is not adequate.
- 78.
It is already a challenge to implement all logic into an 65 nm ASIC for a 50\(\,\cdot \,\)50 \(\upmu \)m\(^2\) cell without sensor electrode and special deep well design rules – see Sect. 1.11.
- 79.
Although, there is no amplification like in gas detectors.
- 80.
Reminder: \(V_{FD }\propto distance^{2}\).
- 81.
The \(n^{++}\) has a higher doping concentration than the deep \(p^{+}\) deep implant.
- 82.
TDC Time to Digital Converter.
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Hartmann, F. (2017). Basic Principles of a Silicon Detector. In: Evolution of Silicon Sensor Technology in Particle Physics. Springer Tracts in Modern Physics, vol 275. Springer, Cham. https://doi.org/10.1007/978-3-319-64436-3_1
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