Comparison of Accelerator Coherency Port (ACP) and High Performance Port (HP) for Data Transfer in DDR Memory Using Xilinx ZYNQ SoC

Abstract

ZYNQ 7000 Embedded Processing Platform SOC is chips includes ARM dual core A9-MPCore Processor Processing System-(PS-Microprocessor) along with Xilinx Programmable Logic (PL)-Artix 7 FPGA on a single die. ZYNQ SoC provides the high performance and computing throughput at low power using PS along with the flexibility of PL. ZYNQ SoC incorporates independent interfaces for communication of data control signals between PL and PS in various configurations to access the system resources. This paper describes the performance evaluation of such interfaces in terms of resource utilization and power consumption. Here, in this paper, data transfer from PL to PS using low speed AXI GP port and high speed bus like AXI HP port and ACP (Accelerator Coherency) port is discussed. The paper includes design, implementation and testing results on Zynq-7000 SoC based Avnet Zed board.