Abstract
This paper proposes a hardware design, implemented on an FPGA, for a hybrid selective encryption and selective error correction coding scheme. FPGA’s are used as implementation platforms in image processing, as its structure exploits the temporal and spatial parallelism. The algorithm aims at implementing security and reliability in which encryption and encoding are performed in a single step using Bezier curve and Galois field GF (2m). The system aims at speeding up the encryption and encoding operations without compromising either on security or on error correcting capability by using selective encryption and selective encoding. The coding for hybrid crypto-coding algorithm is carried out using VHDL. The algorithm is simulated and synthesized using Xilinx ISE 10.1 software. The algorithm is implemented on Spartan 3 FPGA device 3s1000fg676-5. The proposed scheme reduces the hardware as modular arithmetic operations are involved.
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Srividya, B.V., Akhila, S. (2018). Implementing a Hybrid Crypto-coding Algorithm for an Image on FPGA. In: Satapathy, S., Joshi, A. (eds) Information and Communication Technology for Intelligent Systems (ICTIS 2017) - Volume 2. ICTIS 2017. Smart Innovation, Systems and Technologies, vol 84. Springer, Cham. https://doi.org/10.1007/978-3-319-63645-0_8
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DOI: https://doi.org/10.1007/978-3-319-63645-0_8
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