Abstract
This paper proposed the design and implementation of high speed communication link between two FPGAs using LVDS driver using 100 MHz clock. Initially Asynchronous and Synchronous communication are discussed and then synchronous communication is used for LVDS data communication. The speed of the communication is sensitive to the noise and sampling of the data at the receiver end. Therefore, the differential signal voltage level and sampling at the falling edge of clock are proposed in the design to maintain the high speed.
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Shukla, S., Chaudhari, J.P., Nayak, R.J., Mewada, H.K. (2018). Design of High-Speed LVDS Data Communication Link Using FPGA. In: Satapathy, S., Joshi, A. (eds) Information and Communication Technology for Intelligent Systems (ICTIS 2017) - Volume 2. ICTIS 2017. Smart Innovation, Systems and Technologies, vol 84. Springer, Cham. https://doi.org/10.1007/978-3-319-63645-0_1
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DOI: https://doi.org/10.1007/978-3-319-63645-0_1
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