Skip to main content

Designing Reliable Cyber-Physical Systems

  • Chapter
  • First Online:
Book cover Languages, Design Methods, and Tools for Electronic System Design

Abstract

Cyber-physical systems, that consist of a cyber part—a computing system—and a physical part—the system in the physical environment—as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computing system. Here, reliability is a core aspect where some of the most pressing design challenges are:

  • monitoring failures throughout the computing system,

  • determining the impact of failures on the application constraints, and

  • ensuring correctness of the computing system with respect to application-driven requirements rooted in the physical environment.

This chapter gives an overview of the state-of-the-art techniques developed within the Horizon 2020 project IMMORTAL that tackle these challenges throughout the stack of layers of the computing system while tightly coupling the design methodology to the physical requirements. (The chapter is based on the contributions of the special session Designing Reliable Cyber-Physical Systems of the Forum on Specification and Design Languages (FDL) 2016.)

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    Integrated Modelling, Fault Management, Verification and Reliable Design Environment for Cyber-Physical Systems, http://www.h2020-immortal.eu.

  2. 2.

    The semantics of LTL are defined over infinite execution traces; however, we can only run the tests for a finite amount of time. This can result in inconclusive verdicts [9]. To overcome this problem, we refer to existing research on interpreting LTL over finite traces [14, 15, 20].

  3. 3.

    ParSyn-CEGIS, https://github.com/hriener/parsyn-cegis.

References

  1. Abeni, L., & Buttazzo, G. (2004). Resource reservation in dynamic real-time systems. Real-Time System, 27(2), 123–167.

    Article  MATH  Google Scholar 

  2. Ahonen, T., ter Braak, T. D., Burgess, S. T., Geißler, R., Heysters, P. M., Hurskainen, H., et al. (2011). CRISP: Cutting edge reconfigurable ICs for stream processing. In Reconfigurable computing: From FPGAs to hardware/software codesign (pp. 211–237). New York: Springer.

    Chapter  Google Scholar 

  3. Aleksandrowicz, G., Arbel, E., Bloem, R., ter Braak, T. D., Devadze, S., Fey, G., et al. (2016). Designing reliable cyber-physical systems – Overview associated to the special session at FDL’16. In 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14–16, 2016 (pp. 1–8).

    Google Scholar 

  4. Ali, G., Badawy, A., & Kerkhoff, H. G. (2016). On-line management of temperature health monitors using the IEEE 1687 standard. In TESTA (pp. 1–4).

    Google Scholar 

  5. Alur, R., Courcoubetis, C., & Yannakakis, M. (1995). Distinguishing tests for nondeterministic and probabilistic machines. In STOC (pp. 363–372).

    Google Scholar 

  6. Arbel, E., Barak, E., Hoppe, B., Koyfman, S., Krautz, U., & Moran, S. (2016). Gating aware error injection. In HVC (pp. 34–48).

    Google Scholar 

  7. Arbel, E., Koyfman, S., Kudva, P., & Moran, S. (2014). Automated detection and verification of parity-protected memory elements. In ICCAD (pp. 1–8).

    Google Scholar 

  8. Barrett, C. W., Sebastiani, R., Seshia, S. A., & Tinelli, C. (2009). Satisfiability modulo theories. In Handbook of satisfiability (pp. 825–885). Amsterdam: IOS Press.

    Google Scholar 

  9. Bauer, A., Leucker, M., & Schallhart, C. (2011). Runtime verification for LTL and TLTL. TOSEM, 20(4), 14.

    Article  Google Scholar 

  10. Bloem, R., Könighofer, R., Pill, I., & Röck, F. (2016). Synthesizing adaptive test strategies from temporal logic specifications. In FMCAD (pp. 17–24).

    Google Scholar 

  11. Bogomolov, S., Schilling, C., Bartocci, E., Batt, G., Kong, H., & Grosu, R. (2015). Abstraction-based parameter synthesis for multiaffine systems. In HVC (pp. 19–35).

    Google Scholar 

  12. Cimatti, A., Griggio, A., Mover, S., & Tonetta, S. (2013). Parameter synthesis with IC3. In FMCAD (pp. 165–168).

    Google Scholar 

  13. Clarke, E. M., & Emerson, E. A. (1981). Design and synthesis of synchronization skeletons using branching-time temporal logic. In LOP (pp. 52–71).

    Google Scholar 

  14. De Giacomo, G., De Masellis, R., & Montali, M. (2014). Reasoning on LTL on finite traces: Insensitivity to infiniteness. In AAAI (pp. 1027–1033).

    Google Scholar 

  15. De Giacomo, G., & Vardi, M. Y. (2013). Linear temporal logic and linear dynamic logic on finite traces. In IJCAI.

    Google Scholar 

  16. Frehse, S., Fey, G., Arbel, E., Yorav, K., & Drechsler, R. (2012). Complete and effective robustness checking by means of interpolation. In FMCAD (pp. 82–90).

    Google Scholar 

  17. Frehse, G., Jha, S. K., & Krogh, B. H. (2008). A counterexample-guided approach to parameter synthesis for linear hybrid automata. In HSCC (pp. 187–200).

    Google Scholar 

  18. Fraser, G., Wotawa, F., & Ammann, P. (2009). Issues in using model checkers for test case generation. Journal of Systems and Software, 82(9), 1403–1418.

    Article  Google Scholar 

  19. Fraser, G., Wotawa, F., & Ammann, P. (2009). Testing with model checkers: A survey. Software Testing, Verification and Reliability, 19(3), 215–261.

    Article  Google Scholar 

  20. Havelund, K., & Rosu, G. (2001). Monitoring programs using rewriting. In ASE (pp. 135–143).

    Google Scholar 

  21. Hierons, R. M. (2006). Applying adaptive test cases to nondeterministic implementations. Information Processing Letters, 98(2), 56–60.

    Article  MATH  MathSciNet  Google Scholar 

  22. Holcomb, D. E., Li, W., & Seshia, S. A. (2009). Design as you see FIT: System-level soft error analysis of sequential circuits. In DATE (pp. 785–790).

    Google Scholar 

  23. Hölzenspies, P. K. F., ter Braak, T. D., Kuper, J., Smit, G. J. M., & Hurink, J. (2010). Run-time spatial mapping of streaming applications to heterogeneous multi-processor systems. International Journal of Parallel Programming, 38(1), 68–83.

    Article  MATH  Google Scholar 

  24. Ibrahim, A. M. Y., & Kerkhoff, H. G. (2016). An IJTAG-compatible I DDT embedded instrument for health monitoring and prognostics. In ITC, Poster Session.

    Google Scholar 

  25. Jia, Y., & Harman, M. (2011). An analysis and survey of the development of mutation testing. IEEE Transactions on Software Engineering, 37(5), 649–678.

    Article  Google Scholar 

  26. Khan, M. A. (2014). On Improving Dependability of Analog and Mixed-Signal SoCs: A System-Level Approach Ph.D. thesis, University of Twente.

    Google Scholar 

  27. Krautz, U., Pflanz, M., Jacobi, C., Tast, H.-W., Weber, K., & Vierhaus, H. T. (2006). Evaluating coverage of error detection logic for soft errors using formal methods. In DATE (pp. 176–181).

    Google Scholar 

  28. Krishnaswamy, S., Plaza, S., Markov, I. L., & Hayes, J. P. (2009). Signature-based SER analysis and design of logic circuits. IEEE Transactions on Computer-Aided Design, 28(1), 74–86.

    Article  Google Scholar 

  29. Kupferman, O., & Vardi, M. Y. (1997). Synthesis with incomplete information. In ICTL (pp. 91–106).

    Google Scholar 

  30. Lee, E. A., & Seshia, S. A. (2015) Introduction to embedded systems: A Cyber-physical systems approach (2nd ed.). LeeSeshia.org

    MATH  Google Scholar 

  31. Leveugle, R., Calvez, A., Maistri, P., & Vanhauwaert, P. (2009). Statistical fault injection: Quantified error and confidence. In DATE (pp. 502–506).

    Google Scholar 

  32. Maniatakos, M., & Makris, Y. (2010). Workload-driven selective hardening of control state elements in modern microprocessors. In VTS (pp. 159–164).

    Google Scholar 

  33. Mukherjee, S. S., Weaver, C. T., Emer, J. S., Reinhardt, S. K., & Austin, T. M. (2003). A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In MICRO (pp. 29–42).

    Google Scholar 

  34. Nachmanson, L., Veanes, M., Schulte, W., Tillmann, N., & Grieskamp, W. (2004). Optimal strategies for testing nondeterministic systems. In ISSTA (pp. 55–64).

    Google Scholar 

  35. Nicolaidis, M. (2010). Design techniques for soft-error mitigation. In ICICDT (pp. 208–214).

    Google Scholar 

  36. Offutt, A. J. (1992). Investigations of the software testing coupling effect. ACM Transactions on Software Engineering and Methodology, 1(1), 5–20.

    Article  Google Scholar 

  37. Pnueli, A. (1977). The temporal logic of programs. In FOCS (pp. 46–57).

    Google Scholar 

  38. Pnueli, A., & Rosner, R. (1989). On the synthesis of a reactive module. In POPL (pp. 179–190).

    Google Scholar 

  39. Queille, J.-P., & Sifakis, J. (1982). Specification and verification of concurrent systems in CESAR. In PROGRAM (pp. 337–351).

    Google Scholar 

  40. Riener, H., Könighofer, R., Fey, G., & Bloem, R. (2016). SMT-based CPS parameter synthesis. In ARCH@CPSWeek (pp. 126–133).

    Google Scholar 

  41. Saltarelli, P., Niazmand, B., Hariharan, R., Raik, J., Jervan, G., & Hollstein, T. (2015). Automated minimization of concurrent online checkers for network-on-chips. In ReCoSoC (pp. 1–8).

    Google Scholar 

  42. Saltarelli, P., Niazmand, B., Raik, J., Govind, V., Hollstein, T., Jervan, G., et al. (2015). A framework for combining concurrent checking and on-line embedded test for low-latency fault detection in NoC routers. In NOCS (pp. 6:1–6:8).

    Google Scholar 

  43. Seshia, S. A., Li, W., & Mitra, S. (2007). Verification-guided soft error resilience. In DATE (pp. 1442–1447).

    Google Scholar 

  44. Solar-Lezama, A. (2013). Program sketching. International Journal on Software Tools for Technology Transfer, 15(5–6), 475–495.

    Article  Google Scholar 

  45. Sourdis, I., Strydis, C., Armato, A., Bouganis, C.-S., Falsafi, B., Gaydadjiev, G. N., et al. (2013). DeSyRe: On-demand system reliability. Microprocessors and Microsystems, 37(8-C), 981–1001.

    Google Scholar 

  46. Steffens, L., Fohler, G., Lipari, G., & Buttazzo, G. (2003). Resource reservation in real-time operating systems – a joint industrial and academic position. In ARTOSS (pp. 25–30).

    Google Scholar 

  47. ter Braak, T. D. (2014). Using guided local search for adaptive resource re-servation in large-scale embedded systems. In DATE (pp. 1–4).

    Google Scholar 

  48. ter Braak, T. D. (2016). Run-Time Mapping: Dynamic Resource Allocation in Embedded Systems. Ph.D. thesis, University of Twente.

    Google Scholar 

  49. ter Braak, T. D., Toersche, H. A., Kokkeler, A. B. J., & Smit, G. J. M. (2011). Adaptive resource allocation for streaming applications. In SAMOS (pp. 388–395).

    Google Scholar 

  50. Wan, J., & Kerkhoff, H. G. (2015). Embedded instruments for enhancing dependability of analogue and mixed-signal IPs. In NEWCAS (pp. 1–4).

    Google Scholar 

  51. Wan, J., Kerkhoff, H. G., & Bisschop, J. (2016). Simulating NBTI degradation in arbitrary stressed analog/mixed-signal environments. IEEE Transactions on Nanotechnology, 15(2), 137–148.

    Article  Google Scholar 

  52. Yannakakis, M. (2004). Testing, optimizaton, and games. In LICS (pp. 78–88).

    Google Scholar 

  53. Zambrano, A. C., & Kerkhoff, H. G. (2015). Fault-tolerant system for catastrophic faults in AMR sensors. In IOLTS (pp. 65–70).

    Google Scholar 

  54. Zhao, Y., & Kerkhoff, H. G. (2016). A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing. In DTIS (pp. 1–5).

    Google Scholar 

Download references

Acknowledgements

This work was supported in part by the European Union (Horizon 2020 IMMORTAL project, grant no. 644905).

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Jaan Raik .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer International Publishing AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Aleksandrowicz, G. et al. (2018). Designing Reliable Cyber-Physical Systems. In: Fummi, F., Wille, R. (eds) Languages, Design Methods, and Tools for Electronic System Design. Lecture Notes in Electrical Engineering, vol 454. Springer, Cham. https://doi.org/10.1007/978-3-319-62920-9_2

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-62920-9_2

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-62919-3

  • Online ISBN: 978-3-319-62920-9

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics