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Calibration

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High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

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Abstract

Calibration-aided designs are definitely the trend for the state-of-the-art ADCs. They help to improve the performance and save the power of ADCs at low cost. In this chapter, we focus on the calibration techniques for the different ADC architectures. First, the error sources of the pipelined ADC, the SAR ADC, the flash ADC, and the time-interleaved ADC are presented. Second, an overview about the calibration principle is given. Then, we make a step to the calibration schemes of the four architectures. At the end of the chapter, we sum up the calibration techniques of the low-power and high-performance ADC.

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References

  1. M.S. Arthur, H. M. Roermund, Herman Casier, Analog circuit design, (Springer, Netherlands, 2010)

    Google Scholar 

  2. B. Brannon, Sampled systems and the effects of clock phase noise and jitter. Analog Devices Appl. Note, (2004)

    Google Scholar 

  3. H. Wu, Y.P. Xu, A 1v 2.3 \(\mu \)w biomedical signal acquisition ic, in Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International (Feb 2006), pp. 119–128

    Google Scholar 

  4. W. Liu, P. Huang, Y. Chiu, A 12-bit, 45-ms/s, 3-mw redundant successive-approximation-register analog-to-digital converter with digital calibration. Solid-State Circuits, IEEE J. 46, 2661–2672 (2011)

    Article  Google Scholar 

  5. J. Fredenburg, M. Flynn, Statistical analysis of enob and yield in binary weighted adcs and dacs with random element mismatch. Circuits Syst. I: Regul. Pap., IEEE Trans. 59, 1396–1408 (2012)

    Article  MathSciNet  Google Scholar 

  6. M.J.M. Pelgrom, A.C.J. Duinmaijer, Matching properties of mos transistors, in Solid-State Circuits Conference, 1988. ESSCIRC ’88. Fourteenth European (Sept 1988), pp. 327–330

    Google Scholar 

  7. R.W. Gregor, On the relationship between topography and transistor matching in an analog cmos technology. IEEE Trans. Electron Devices 39, 275–282 (1992)

    Article  Google Scholar 

  8. J.B. Shyu, G.C. Temes, F. Krummenacher, Random error effects in matched mos capacitors and current sources. IEEE J. Solid-State Circuits 19, 948–956 (1984)

    Article  Google Scholar 

  9. M. Armstrong, H. Ohara, H. Ngo, C. Rahim, A. Grossman, P. Gray, A cmos programmable self-calibrating 13b eight-channel analog interface processor, in Solid-State Circuits Conference Digest of Technical Papers. 1987 IEEE International (Feb 1987), pp. 44–45

    Google Scholar 

  10. K.S. Tan, S. Kiriaki, M. de Wit, J.W. Fattaruso, C.Y. Tsay, W.E. Matthews, R.K. Hester, Error correction techniques for high-performance differential a/d converters. IEEE J. Solid-State Circuits 25, 1318–1327 (1990)

    Article  Google Scholar 

  11. Y. M. Lin, B. Kim, and P.R. Gray, A 13 bit 2.5 mhz self-calibrated pipelined a/d converter in 3-\(\mu \)m cmos, in VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on (June 1990), pp. 33–34

    Google Scholar 

  12. P.W. Li, M.J. Chin, P.R. Gray, R. Castello, A ratio-independent algorithmic analog-to-digital conversion technique. IEEE J. Solid-State Circuits 19, 828–836 (1984)

    Article  Google Scholar 

  13. H.S. Lee, D.A. Hodges, P.R. Gray, A self-calibrating 15 bit cmos a/d converter. IEEE J. Solid-State Circuits 19, 813–819 (1984)

    Article  Google Scholar 

  14. H.-S. Chen, K. Bacrania, and B.-S. Song, A 14 b 20 msample/s cmos pipelined adc, in Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International (Feb 2000), pp. 46–47

    Google Scholar 

  15. Y. Chiu, Inherently linear capacitor error-averaging techniques for pipelined a/d conversion. IEEE Trans. Circuits Syst. II: Analog Digital Signal Proc. 47, 229–232 (2000)

    Article  Google Scholar 

  16. S.H. Lee, B.S. Song, A direct code error calibration technique for two-step flash a/d converters. IEEE Trans. Circuits Syst. 36, 919–922 (1989)

    Article  Google Scholar 

  17. S.U. Kwak, B.S. Song, K. Bacrania, A 15-b, 5-msample/s low-spurious cmos adc. IEEE J. Solid-State Circuits 32, 1866–1875 (1997)

    Article  Google Scholar 

  18. A.N. Karanicolas, H.-S. Lee, K.L. Barcrania, A 15-b 1-msample/s digitally self-calibrated pipeline adc. IEEE J. Solid-State Circuits 28, 1207–1215 (1993)

    Article  Google Scholar 

  19. O.E. Erdogan, P.J. Hurst, S.H. Lewis, A 12-b digital-background-calibrated algorithmic adc with -90-db thd. IEEE J. Solid-State Circuits 34, 1812–1820 (1999)

    Article  Google Scholar 

  20. D.-Y. Chang, J. Li, U.-K. Moon, Radix-based digital calibration techniques for multi-stage recycling pipelined adcs. IEEE Trans. Circuits Syst. I: Regul. Pap. 51, 2133–2140 (2004)

    Article  Google Scholar 

  21. U.-K. Moon, B.-S. Song, Background digital calibration techniques for pipelined adcs. IEEE Trans. Circuits Syst. II: Analog Digital Signal Proc. 44, 102–109 (1997)

    Article  Google Scholar 

  22. A.J. Gines, E.J. Peralias, and A. Rueda, Improved background algorithms for pipeline adc full calibration, in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on (May 2007), pp. 3383–3386

    Google Scholar 

  23. D. Morin, Y. Savaria, M. Sawan, A 200 msps 10-bit pipelined adc using digital calibration, in IEEE-NEWCAS Conference, 2005. The 3rd International (June 2005), pp. 67–70

    Google Scholar 

  24. U. Eduri, F. Maloberti, Online calibration of a nyquist-rate analog-to-digital converter using output code-density histograms. IEEE Trans. Circuits Syst. I: Regul. Pap. 51, 15–24 (2004)

    Article  Google Scholar 

  25. I. Ahmed and D.A. Johns, An 11-bit 45ms/s pipelined adc with rapid calibration of dac errors in a multi-bit pipeline stage, in Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European (Sept 2007), pp. 147–150

    Google Scholar 

  26. J. Li, U.-K. Moon, Background calibration techniques for multistage pipelined adcs with digital redundancy. IEEE Trans. Circuits Syst. II: Analog Digital Signal Proc. 50, 531–538 (2003)

    Article  Google Scholar 

  27. L. Brooks, H.S. Lee, Background calibration of pipelined adcs via decision boundary gap estimation. IEEE Trans. Circuits Syst. I: Regul. Pap. 55, 2969–2979 (2008)

    Article  MathSciNet  Google Scholar 

  28. W. Li, C. Sun, F. Li, and Z. Wang, A 14-bit pipelined adc with digital background nonlinearity calibration, in Circuits and Systems (ISCAS), 2013 IEEE International Symposium on (May 2013), pp. 2448–2451,

    Google Scholar 

  29. S. Li, W. Li, F. Li, Z. Wang, C. Zhang, A digital blind background calibration algorithm for pipelined adc, in 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS) (June 2015), pp. 1–4

    Google Scholar 

  30. C. Yang, F. Li, W. Li, X. Wang, Z. Wang, An 85mw 14-bit 150ms/s pipelined adc with 71.3db peak sndr in 130nm cmos, in Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian (Nov 2013), pp. 85–88

    Google Scholar 

  31. Y. Kuramochi, A. Matsuzawa, M. Kawabata, A 0.05-\(mm^2\) 110-\(\mu \)w 10-b self-calibrating successive approximation adc core in 0.18-\(\mu \)m cmos, in Solid-State Circuits Conference, 2007. ASSCC ’07. IEEE Asian (Nov 2007), pp. 224–227

    Google Scholar 

  32. L. Sun, K.P. Pun, A. Wong, Analysis and design of a 14-bit sar adc using self-calibration dac, in Circuits and Systems (ISCAS), 2012 IEEE International Symposium on (May 2012), pp. 1267–1270

    Google Scholar 

  33. M. Yoshioka, K. Ishikawa, T. Takayama, S. Tsukamoto, A 10b 50ms/s 820 \(\mu \)w sar adc with on-chip digital calibration, in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International (Feb 2010), pp. 384–385

    Google Scholar 

  34. Y. Ju, F. Li, X. Gu, C. Zhang, Z. Wang, Digital calibration technique for subrange adc based on sar architecture, in 2016 5th International Symposium on Next-Generation Electronics (ISNE) (May 2016), pp. 1–2

    Google Scholar 

  35. X. Gu, X. He, F. Li, A calibration technique for sar adc based on code density test, in 2015 IEEE 11th International Conference on ASIC (ASICON) (Nov 2015), pp. 1–4

    Google Scholar 

  36. X. Zhu, Y. Chen, S. Tsukamoto, T. Kuroda, A 9-bit 100ms/s tri-level charge redistribution sar adc with asymmetric cdac array, in Proceedings of Technical Program of 2012 VLSI Design, Automation and Test (Apr 2012), pp. 1–4

    Google Scholar 

  37. J.Y. Um, Y.J. Kim, E.W. Song, J.Y. Sim, H.J. Park, A digital-domain calibration of split-capacitor dac for a differential sar adc without additional analog circuits. IEEE Trans. Circuits and Syst. I: Regul. Pap. 60, 2845–2856 (2013)

    Article  Google Scholar 

  38. B. Razavi, B.A. Wooley, Design techniques for high-speed, high-resolution comparators. IEEE J. Solid-State Circuits 27, 1916–1926 (1992)

    Article  Google Scholar 

  39. C.Y. Chen, M.Q. Le, K.Y. Kim, A low power 6-bit flash adc with reference voltage and common-mode calibration. IEEE J. Solid-State Circuits 44, 1041–1046 (2009)

    Article  Google Scholar 

  40. J. Wu, F. Li, W. Li, C. Zhang, Z. Wang, A 14-bit 200ms/s low-power pipelined flash-sar adc, in 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) (Aug 2015), pp. 1–4

    Google Scholar 

  41. S. Park, Y. Palaskas, M.P. Flynn, A 4gs/s 4b flash adc in 0.18/spl mu/m cmos, in 2006 IEEE International Solid State Circuits Conference-Digest of Technical Papers (Feb 2006), pp. 2330–2339

    Google Scholar 

  42. E. Alpman, H. Lakdawala, L.R. Carley, K. Soumyanath, A 1.1v 50mw 2.5gs/s 7b time-interleaved c-2c sar adc in 45nm lp digital cmos, in 2009 IEEE International Solid-State Circuits Conference-Digest of Technical Papers (Feb 2009), pp. 76–77,77a

    Google Scholar 

  43. M. Miyahara, Y. Asada, D. Paik, A. Matsuzawa, A low-noise self-calibrating dynamic comparator for high-speed adcs, in Solid-State Circuits Conference, 2008. A-SSCC ’08. IEEE Asian (Nov 2008), pp. 269–272

    Google Scholar 

  44. J. Mei, X. Shen, H. Zhou, F. Ye, J. Ren, A low kickback noise and offset calibrated dynamic comparator for 2b/c sar adc, in Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on (Oct 2014), pp. 1–3

    Google Scholar 

  45. L. Sun, K.P. Pun, Low-offset comparator using capacitive self-calibration, in SoC Design Conference (ISOCC), 2012 International (Nov 2012), pp. 412–414

    Google Scholar 

  46. C.H. Chan, Y. Zhu, U.F. Chio, S.W. Sin, U. Seng-Pan, and R.P. Martins, A reconfigurable low-noise dynamic comparator with offset calibration in 90nm cmos, in Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian (Nov 2011), pp. 233–236

    Google Scholar 

  47. G.V. der Plas, S. Decoutere, S. Donnay, A 0.16pj/conversion-step 2.5mw 1.25gs/s 4b adc in a 90nm digital cmos process, in 2006 IEEE International Solid State Circuits Conference-Digest of Technical Papers (Feb 2006), pp. 2310

    Google Scholar 

  48. S. Jamal et al., A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration. IEEE J. Solid-State Circuits 37, 1618–1627 (2002)

    Article  Google Scholar 

  49. C.-C. Hsu et al., An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration, in IEEE International Solid State Circuits Conference-Digest of Technical Papers (Feb 2007), pp. 464–615

    Google Scholar 

  50. D. Stepanovic, B. Nikolic, A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS. IEEE J. Solid-State Circuits 48, 971–982 (2013)

    Article  Google Scholar 

  51. C.-Y. Wang, J.-T. Wu, A multiphase timing-skew calibration technique using zero-crossing detection. IEEE Trans. Circuits Syst. I: Regul. Pap. 56, 1102–1114 (2009)

    Article  MathSciNet  Google Scholar 

  52. M. El-Chammas, B. Murmann, A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration. IEEE J. Solid-State Circuits 46, 838–847 (2011)

    Article  Google Scholar 

  53. S. Tertinek, C. Vogel, Reconstruction of nonuniformly sampled bandlimited signals using a differentiator-multiplier cascade. IEEE Trans. Circuits Syst. I: Regul. Pap. 55, 2273–2286 (2008)

    Article  MathSciNet  Google Scholar 

  54. X. Wang, F. Li, Z. Wang, A novel autocorrelation-based timing mismatch c alibration strategy in time-interleaved adcs, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS) (May 2016), pp. 1490–1493

    Google Scholar 

  55. M. El-Chammas and B. Murmann, Background Calibration of Time-interleaved Data Converters. (Springer, 2012)

    Google Scholar 

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Authors and Affiliations

  1. Institute of Microelectronics, Tsinghua University, Beijing, China

    Weitao Li, Fule Li & Zhihua Wang

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  1. Weitao Li
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  2. Fule Li
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  3. Zhihua Wang
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Correspondence to Weitao Li .

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Li, W., Li, F., Wang, Z. (2018). Calibration. In: High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications . Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-62012-1_6

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  • DOI: https://doi.org/10.1007/978-3-319-62012-1_6

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-62011-4

  • Online ISBN: 978-3-319-62012-1

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