Abstract
In different architectures introduced throughout the years, the comparator is a necessary circuit block. It plays an important role not only in the accuracy, but also in the speed of the data conversion. In this chapter, we discuss how to provide a comparator for a power-efficient and high-performance ADC. First, the circuit techniques that help to relax the requirements of the comparator are presented. Both the redundancy technique and the reference voltage stabilization technique are described. Second, we make a step to the design considerations of the dynamic comparator, including the speed and power dissipation, the noise , the offset , and the kickback noise . At the end of the chapter, we sum up the comparator design for the power-efficient and high-performance ADC.
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Li, W., Li, F., Wang, Z. (2018). Comparator. In: High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications . Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-62012-1_5
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DOI: https://doi.org/10.1007/978-3-319-62012-1_5
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Online ISBN: 978-3-319-62012-1
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