A Scalable and Low-Power FPGA-Aware Network-on-Chip Architecture

Abstract

The growing demand for high-performance capabilities in data centers (DCs) leads to adopt heterogeneous solutions. The advantage of specialised hardware is a better support for different types of workloads, and a reduction of the power consumption. Among the others, FPGAs offer the unique capability to provide hardware specialisation and low power consumption. In this context, large arrays of simple and reconfigurable processing elements (PEs), known as coarse-grain reconfigurable arrays (CGRAs), represent a flexible solution for supporting heterogeneous workloads through a specialised instruction set that provides high performance in specific application domains (e.g., image recognition, patterns classification). However, efficient and scalable interconnections are required to sustain throughput and performance of CGRAs. To this end, networks-on-chip (NoCs) have been recognised as a viable solution for better data packet communication. In this paper, we propose an FPGA-aware NoC design targeting CGRAs with 128+ PEs. The proposed design leverages on a two-level topology to scale well with the increasing number of PEs, while the introduction of a software-defined reconfiguration capability offers the opportunity to tailor the set of resources assigned to a specific application. Partitions of physical resources (i.e., virtual domains) are built over the physical topology to meet the required performance, as well as to ease sharing physical chip resources among applications. Experimental evaluation shows the efficiency of our solution regarding used FPGA resources and power consumption.

S. Mazumdar and A. Scionti—Both the authors contributed equally.