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Introduction

  • Muhammad Usman Karim Khan
  • Muhammad Shafique
  • Jörg Henkel
Chapter

Abstract

High-density, nanoscale fabrication technologies have enabled the chip designers to assemble billions of transistors on a single die. This has in turn provided the capability to realize high-complexity systems like video systems, which have universally penetrated into communication, security, education, entertainment, navigation, and robotics domains. The advancement in the fabrication technology has also driven the user expectations of the next-generation video processing systems. A prime example is high-resolution video capture and playback. Therefore, video applications like the latest video encoders [1] now target high-resolution video content compression beyond full-HD (like 4K ultrahigh definition, 3840 × 2160 pixels) at high frame rates (>120 frames per second). On the contrary, emergence and evolution of next-generation video systems (with increasing throughput and connectivity requirements and adaptability to application, battery life, etc.) require high processing capabilities and efficient utilization of the resources, which might be prohibitive on a resource- and power-constraint hardware platform. Though high-end systems can meet the throughput requirements, efficient and long-term deployment of such applications on small, battery-driven, autonomous systems is challenging, due to the high computational and power requirements while addressing the throughput constraints. Coupled with the high-throughput demands, a video system must be capable of responding in real time to changes in the workload of the application. Further, modern nano-era fabrication technologies have their own associated challenges (like power wall [2] and reliability [3]) which must be accounted for forging energy-efficient multimedia systems. This suggests that new design methodologies for next-generation video systems are needed, to address the abovementioned challenges on modern systems. This book presents some of these methodologies, both at the software and hardware layers of the system.

References

  1. 1.
    Sullivan, G. J., Ohm, J., Han, W., & Wiegand, T. (2012). Overview of high efficiency video coding. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1649–1668.CrossRefGoogle Scholar
  2. 2.
    Esmaeilzadeh, H., Blem, E., Amant, R., Sankaralingam, K., & Burger, D. (2011). Dark silicon and the end of multicore scaling. In International Symposium on Computer Architecture (ISCA).Google Scholar
  3. 3.
    Henkel, J., Bauer, L., Dutt, N., Gupta, P., Nassif, S., Shafique, M., Tahoori, M., & Wehn, N. (2013). Reliable on-chip systems in the nano-era: Lessons learnt and future trends. In Design Automation Conference (DAC).Google Scholar
  4. 4.
    ARTEMIS, [Online]. Available: http://www.artemis-ju.eu/embedded_systems. Accessed 20 Oct 2015.
  5. 5.
    Shafique, M. (2011). Architectures for adaptive low-power embedded multimedia systems. Karlsruhe Institute of Technology (KIT).Google Scholar
  6. 6.
    Nister, D. (2004). Automatic passive recovery of 3D from images and video. In International Symposium on 3D Data Processing, Visualization and Transmission.Google Scholar
  7. 7.
    Cutrona, L., Leith, E., Porcello, L., & Vivian, W. (1966). On the application of coherent optical processing techniques to synthetic-aperture radar. Proceedings of the IEEE, 54(8), 1026–1032.CrossRefGoogle Scholar
  8. 8.
    WebRTC. [Online]. Available: http://www.webrtc.org/. Accessed 26 Aug 2015.
  9. 9.
    AdReaction. Marketing in a multiscreen world [Online]. Available: https://www.millwardbrown.com/adreaction/2014/report/Millward-Brown_AdReaction-2014_Global.pdf. Accessed 12 July 2017.
  10. 10.
    Intel chips through the years. (2015, September 12). [Online]. Available: http://interestingengineering.com/intel-chips-timeline/. Accessed 5 Oct 2015.
  11. 11.
    Held, J. (2010). Introducing the single-chip cloud computer: exploring the future of many-core processors. In Intel White Paper.Google Scholar
  12. 12.
    Pathania, A., Pagani, S., Shafique, M., & Henkel, J. (2015). Power management for mobile games on asymmetric multi-cores. In Low Power Electronics and Design (ISLPED).Google Scholar
  13. 13.
    Momcilovic, S., Ilic, A., Roma, N., & Sousa, L. (2014). Dynamic load balancing for real-time video encoding on heterogeneous CPU+GPU systems. IEEE Transactions on Multimedia, 16(1), 108–121.CrossRefGoogle Scholar
  14. 14.
    Xiao, W., Li, B., Xu, J., Shi, G., & Wu, F. (2015). HEVC encoding optimization using multi-core CPUs and GPUs. IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), 9(99), 1–14.Google Scholar
  15. 15.
    Khan, M., Shafique, M., Bauer, L., & Henkel, J. (2015). Multicast FullHD H.264 intra video encoder architecture. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1–5.Google Scholar
  16. 16.
    Benkrid, K., Crookes, D., Smith, J., & Benkrid, A. (2000). High level programming for real time FPGA based video processing. In Acoustics, Speech, and Signal Processing (ICASSP).Google Scholar
  17. 17.
    Iwata, K., Mochizuki, S., Kimura, M., Shibayama, T., Izuhara, F., Ueda, H., Hosogi, K., Nakata, H., Ehama, M., Kengaku, T., Nakazawa, T., & Watanabe, H. (2009). A 256 mW 40 Mbps Full-HD H.264 high-profile codec featuring a dual-macroblock pipeline architecture in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 44(4), 1184–1191.CrossRefGoogle Scholar
  18. 18.
    Zhou, J., Zhou, D., Fei, W., & Goto, S. (2013). A high-performance CABAC encoder architecture for HEVC and H.264/AVC. In International Conference on Image Processing (ICIP).Google Scholar
  19. 19.
    Henkel, J., & Yanbing, L. (1998). Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder. In International Workshop on Hardware/Software Codesign.Google Scholar
  20. 20.
    Zuluaga, M., & Topham, N. (2009). Design-space exploration of resource-sharing solutions for custom instruction set extensions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 28(12), 1788–1801.CrossRefGoogle Scholar
  21. 21.
    Grudnitsky, A., Bauer, L., & Henkel, J. (2014). COREFAB: Concurrent reconfigurable fabric utilization in heterogeneous multi-core systems. In International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).Google Scholar
  22. 22.
    Majer, M., Teich, J., Ahmadinia, A., & Bobda, C. (2007). The erlangen slot machine: A dynamically reconfigurable FPGA-based computer. VLSI Signal Processing Systems for Signal, Image, and Video Technology, 47(1), 15–31.CrossRefGoogle Scholar
  23. 23.
    Smith, C. 120 Amazing YouTube statistics. [Online]. .Available: http://expandedramblings.com/index.php/youtube-statistics/. Accessed 5 Oct 2015.
  24. 24.
    Dong, X., Wu, X., Sun, G., Xie, Y., Li, H., & Chen, Y. (2008). Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In Design Automation Conference (DAC).Google Scholar
  25. 25.
    Wu, X., Li, J., Zhang, L., Speight, E., Rajamony, R., & Xie, Y. (2009). Hybrid cache architecture with disparate memory technologies. In International Symposium on Computer Architecture (ISCA).Google Scholar
  26. 26.
    Joint Collaborative Team on Video Coding (JCT-VC), ITU, [Online]. Available: http://www.itu.int/en/ITU-T/studygroups/2013-2016/16/Pages/video/jctvc.aspx. Accessed 7 Oct 2015.
  27. 27.
    Ostermann, J., Bormans, J., List, P., Marpe, D., Narroschke, M., Pereira, F., Stockhammer, T., & Wedi, T. (2004). Video coding with H.264/AVC: Tools, performance, and complexity. IEEE Circuits and Systems Magazine, 4(1), 7–28.CrossRefGoogle Scholar
  28. 28.
    Grois, D., Marpe, D., Mulayoff, A., Itzhaky, B., & Hadar, O. (2013). Performance comparison of H.265/MPEG-HEVC, VP9, and H.264/MPEG-AVC encoders. In Picture Coding Symposium (PCS).Google Scholar
  29. 29.
    Girod, B., Aaron, A. M., Rane, S., & Rebollo-Monedero, D. (2005). Distributed Video Coding. Proceedings of the IEEE, 93(1), 71–83.CrossRefzbMATHGoogle Scholar
  30. 30.
    Dufaux, F., & Ebrahimi, T. (2010). Encoder and decoder side global and local motion estimation for Distributed Video Coding. In International Workshop on Multimedia Signal Pro-cessing.Google Scholar
  31. 31.
    Huang, W., Rajamani, K., Stan, M., & Skadron, K. (2011). Scaling with design constraints: Predicting the future of big chips. IEEE Micro, 31(4), 16–29.CrossRefGoogle Scholar
  32. 32.
    Bohr, M. (2007). A 30 year retrospective on dennard’s mosfet scaling paper. IEEE Solid-State Circuits Society Newsletter, 12(1), 11–13.CrossRefGoogle Scholar
  33. 33.
    Khan, M., Shafique, M., & Henkel, J. (2013). An adaptive complexity reduction scheme with fast prediction unit decision for HEVC intra encoding. In International Conference on Image Processing (ICIP).Google Scholar
  34. 34.
    Khan, M., Shafique, M., & Henkel, J. (2013). AMBER: Adaptive energy management for on-chip hybrid video memories. In International Conference on Computer-Aided Design (ICCAD).Google Scholar
  35. 35.
    Dennard, R., Rideout, V., Bassous, E., & LeBlanc, A. (1974). Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE Journal of Solid-State Circuits, 9(5), 256–268.CrossRefGoogle Scholar
  36. 36.
    Huck, S. (2011). Measuring processor power, TDP vs. ACP. Intel.Google Scholar
  37. 37.
    Ghemawat, S., Gobioff, H., & Leung, S.-T. (2003). The google file system. In ACM Symposium on Operating Systems Principles.Google Scholar
  38. 38.
    Kumar, S., Kim, C., & Sapatnekar, S. (2006). Impact of NBTI on SRAM read stability and design for reliability. In International Symposium on Quality Electronic Design (ISQED).Google Scholar
  39. 39.
    Gnad, D., Shafique, M., Kriebel, F., Rehman, S., Sun, D., & Henkel, J. (2015). Hayat: Harnessing dark silicon and variability for aging deceleration and balancing. In 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).Google Scholar
  40. 40.
    Khan, M. U. K., Shafique, M., & Henkel, J. (2014). Software architecture of high efficiency video coding for many-core systems with power-efficient workload balancing. In Design, Automation and Test in Europe.Google Scholar
  41. 41.
    Khan, M. U. K., Shafique, M., Gupta, A., Schumann, T., & Henkel J. (2016). Power-efficient load-balancing on heterogeneous computing platforms. In IEEE/ACM 19th Design, Automation and Test in Europe Conference (DATE).Google Scholar
  42. 42.
    Shafique, M., Khan, M. U. K., & Henkel, J. (2014). Power efficient and workload balanced tiling for parallelized high efficiency video coding. In International Conference on Image Processing.Google Scholar
  43. 43.
    Khan, M. U. K., Shafique, M., & Henkel, J. (2015). Hierarchical power budgeting for dark silicon chips. In International Symposium on Low Power Electronics and Design.Google Scholar
  44. 44.
    Khan, M. U. K., Shafique, M., & Henkel, J. (2014). Fast hierarchical intra angular mode selection for high efficiency video coding. In International Conference on Image Processing.Google Scholar
  45. 45.
    Khan, M. U. K., Borrmann, J. M., Bauer, L., Shafique, M., & Henkel, J. (2013). An H.264 Quad-FullHD low-latency intra video encoder. In Design, Automation & Test in Europe Conference & Exhibition (DATE).Google Scholar
  46. 46.
    Khan, M. U. K., Shafique, M., & Henkel, J. (2013). Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder. In Design, Automation and Test in Europe (DATE).Google Scholar
  47. 47.
    Khan, M. U. K., Shafique, M., & Henkel, J. (2015). Power-efficient accelerator allocation in adaptive dark silicon many-core systems. In Design, Automation & Test in Europe Conference & Exhibition (DATE).Google Scholar
  48. 48.
    Shafique, M., Khan, M. U. K., Tüfek, O., & Henkel, J. (2015). EnAAM: Energy-efficient anti-aging for on-chip video memories. In Design Automation Conference (DAC).Google Scholar
  49. 49.
    Shafique, M., Khan, M. U. K., & Henkel, J. (2016). Content-aware low-power configurable aging mitigation for SRAM memories. IEEE Transactions on Computers (TC), 65(12), 36173630.MathSciNetCrossRefzbMATHGoogle Scholar

Copyright information

© Springer International Publishing AG 2018

Authors and Affiliations

  • Muhammad Usman Karim Khan
    • 1
  • Muhammad Shafique
    • 2
  • Jörg Henkel
    • 3
  1. 1.IBM Deutschland Research & Development GmbHBöblingenGermany
  2. 2.Institute of Computer EngineeringVienna University of TechnologyViennaAustria
  3. 3.Department of Computer ScienceKarlsruhe Institute of TechnologyKarlsruheGermany

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