Abstract
This paper presents a dynamic zoom ADC for audio applications. It achieves 109-dB DR, 106-dB SNR, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating 1.12 mW and occupying only 0.16 mm2 in 0.16-μm CMOS. This translates to state-of-the-art energy and area efficiency. In this paper, the system- and circuit-level design of the ADC will be presented.
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Notes
- 1.
While it is trivial that lower thermal noise requires larger capacitors in DT circuits, this is also true for continuous-time circuits: lower thermal noise implies lower resistances and, consequently, larger capacitors for the same total bandwidth.
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Gönen, B., Sebastiano, F., van Veldhoven, R., Makinwa, K.A.A. (2018). A Hybrid ADC for High Resolution: The Zoom ADC. In: Harpe, P., Makinwa, K., Baschirotto, A. (eds) Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-319-61285-0_6
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DOI: https://doi.org/10.1007/978-3-319-61285-0_6
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