Abstract
While conventional flash, pipelined, successive-approximation-register (SAR), and ΔΣ analog-to-digital converters (ADCs) have demonstrated a fundamental trade-off between speed and resolution, a recent trend of hybrid ADCs nicely blends different architectures into one ADC design, enabling new breakthroughs in resolution, speed, area, and power efficiency. The mixture of multiple ADC architectures also opens up a new possibility to configure an ADC across a wide speed and resolution range. This paper introduces a SAR-based hybrid design incorporating with a hybrid DAC linearization scheme to extend the application of a power-efficient SAR ADC for high-resolution sensor readout interfaces. This architecture allows an ADC to be configured between SAR- and ΔΣ-type performance with flexible sampling rate and is especially suitable for various Internet of Things (IoT) sensor applications.
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Shu, YS., Kuo, LT., Lo, TY. (2018). A Hybrid Architecture for a Reconfigurable SAR ADC. In: Harpe, P., Makinwa, K., Baschirotto, A. (eds) Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-319-61285-0_5
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DOI: https://doi.org/10.1007/978-3-319-61285-0_5
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