Abstract
An example of usage of ADC hybrid techniques and DAC segmented topologies to achieve high power efficiency and low total area is presented. The resulting hybrid ADC architecture consisting of a coarse SAR ADC followed by an incremental ΔΣ fine converter provides better suppression of thermal noise added during conversion for a given power compared to a conventional SAR. The usage of a segmented charge-sharing charge-redistribution DAC scheme enables significant area saving compared to conventional DAC topologies. The 28 nm 600 MS/s four-way interleaved prototype ADC achieves an SNDR of 60.7 dB and 58 dB at low and high frequency, respectively, while consuming only 26 mW for a total area of 0.076 mm2.
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Venca, A., Ghittori, N., Bosi, A., Nani, C. (2018). Hybrid and Segmented ADC Techniques to Optimize Power Efficiency and Area: The Case of a 0.076 mm2 600 MS/s 12b SAR-ΔΣ ADC. In: Harpe, P., Makinwa, K., Baschirotto, A. (eds) Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-319-61285-0_2
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DOI: https://doi.org/10.1007/978-3-319-61285-0_2
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