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Pipeline and SAR ADCs for Advanced Nodes

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Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design

Abstract

The switched-capacitor SAR architecture has benefited tremendously from technology scaling. We first present a charge-injection-based SAR architecture that shrinks the die area needed for a SAR ADC and achieves outstanding energy efficiency. We go on to discuss pipeline ADCs using SAR sub-ADCs and a ring amplifier. We present a SAR- assisted pipeline that achieves record efficiency for >12-bit pipeline ADCs. We argue that SAR ADCs are among the most efficient stand-alone converters for advanced nodes and an important building block for other converters.

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References

  1. Murmann, B.: Energy limits in current A/D converter architectures, ISSCC Short Course, Feb. 2012

    Google Scholar 

  2. Lee, C.C., Flynn, M.P.: A SAR-assisted two-stage pipeline ADC. IEEE JSSC. 46(4), 859–869 (2011)

    Google Scholar 

  3. Choo, K.D., Bell, J., Flynn, M.P.: Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC. ISSCC Digest Technical Papers. 460–461 (Feb. 2016)

    Google Scholar 

  4. Lim, Y., Flynn, M.P.: A 1 mW 71.5 dB SNDR 50 MS/s 13 bit fully differential ring amplifier based SAR-assisted pipeline ADC. IEEE JSSC. 50(12), 2901–2911 (2015)

    Google Scholar 

  5. Le Dortz, N., et al.: A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS. ISSCC Digest Technical Papers. 386–388 (Feb. 2014)

    Google Scholar 

  6. Chan, C.-H., et al.: A 5.5mW 6b 5GS/S 4×−interleaved 3b/cycle SAR ADC in 65nm CMOS. In ISSCC Digest Technical Papers, pp. 1, 3, Feb. 2015

    Google Scholar 

  7. Hong, H-K., et al.: An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement. In ISSCC Digest Technical Papers, pp. 470, 471, Feb. 2013

    Google Scholar 

  8. Liu, C.-C., et al.: A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process. IEEE Symposium VLSI Circuits, Digest Technical Papers, pp. 236–237, June 2009

    Google Scholar 

  9. Yang, W.H., Kelly, D., Mehr, I., Sayuk, M.T., Singer, L.: A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE JSSC. 36, 1931–1936 (2001)

    Google Scholar 

  10. Devarajan, S., Singer, L., Kelly, D., Decker, S., Kamath, A., Wilkins, P.: A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC. IEEE ISSCC Digest Technical Papers. 86–87 (Feb. 2009)

    Google Scholar 

  11. Lee, H.-Y., Lee, B., Moon, U.-K.: A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS. In IEEE ISSCC Digest Technical Papers, pp. 474–475, Feb. 2012

    Google Scholar 

  12. Verbruggen, B., Iriguchi, M., Craninckx, J.: A 1.7 mW 11b 250 MS/s 2-times interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS. IEEE JSSC. 47(12), 2880–2887 (2012)

    Google Scholar 

  13. Verbruggen, B. et al.: A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS. IEEE Symposium VLSI Circuits, Digest Technical Papers, pp. 268–269, June 2013

    Google Scholar 

  14. van der Goes, F., et al.: A 1.5 mW 68 dB SNDR 80 Ms/s 2 × interleaved pipelined SAR ADC in 28 nm CMOS. IEEE JSSC. 49(12), 2835–2845 (2014)

    Google Scholar 

  15. Verbruggen, B., Deguchi, K., Malki, B., Craninckx, J.: A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS. In: IEEE Symp. VLSI Circuits, Digest Technical Papers, pp. 268–269, June 2014

    Google Scholar 

  16. Malki, B., Verbruggen, B., Wambacq, P., Deguchi, K., Iriguchi, M., Craninckx, J.: A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. In: ESSCIRC Digest Technical Papers, pp. 215–218, Sep. 2014

    Google Scholar 

  17. Hershberg, B., Weaver, S., Sobue, K., Takeuchi, S., Hamashita, K., Moon, U.-K.: Ring amplifiers for switched capacitor circuits. IEEE JSSC. 47(12), 2928–2942 (2012)

    Google Scholar 

  18. Lim, Y., Flynn, M.P.: A 100 MS/s, 10.5 bit, 2.46 mW comparator-less pipeline ADC using self-biased ring amplifiers. IEEE JSSC. 50(10), 2331–2341 (2015)

    Google Scholar 

  19. Razavi, B.: Operational amplifiers. In: Design of Analog CMOS Integrated Circuits, pp. 319–324. McGraw-Hill, Boston (2001)

    Google Scholar 

  20. Hariprasath, V., Guerber, J., Lee, S.-H., Moon, U.-K.: Merged capacitor switching based SAR ADC with highest switching energy-efficiency. Electron. Lett. 46(9), 620–621 (2010)

    Article  Google Scholar 

  21. Chen, S.-W., Brodersen, R.W.: A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13μm CMOS. IEEE ISSCC Digest Technical Papers. 2350–2351 (Feb. 2006)

    Google Scholar 

  22. Tai, H.-Y., Hu, Y.-S., Chen, H.-W., Chen, H.-S.: A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS. IEEE ISSCC Digest Technical Papers. 196–197 (Feb. 2014)

    Google Scholar 

  23. Enz, C.C., Temes, G.C.: Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization. Proc. IEEE. 84(11), 1584–1614 (1996)

    Article  Google Scholar 

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Authors and Affiliations

  1. University of Michigan, 1301 Beal Ave, Ann Arbor, MI, 48109, USA

    Michael P. Flynn, Kyojin Choo & Yong Lim

Authors
  1. Michael P. Flynn
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  2. Kyojin Choo
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  3. Yong Lim
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Corresponding author

Correspondence to Michael P. Flynn .

Editor information

Editors and Affiliations

  1. Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, Noord-Brabant, The Netherlands

    Pieter Harpe

  2. Department of Microelectronics, Delft University of Technology, Delft, Zuid-Holland, The Netherlands

    Kofi A. A. Makinwa

  3. Department of Physics G. Occhialini, University of Milan, Milano, Italy

    Andrea Baschirotto

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Flynn, M.P., Choo, K., Lim, Y. (2018). Pipeline and SAR ADCs for Advanced Nodes. In: Harpe, P., Makinwa, K., Baschirotto, A. (eds) Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-319-61285-0_16

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  • DOI: https://doi.org/10.1007/978-3-319-61285-0_16

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-61284-3

  • Online ISBN: 978-3-319-61285-0

  • eBook Packages: EngineeringEngineering (R0)

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