Abstract
This chapter presents novel gain-cell based embedded dynamic random-access memory (GC-eDRAM) bitcells and assist techniques specifically designed to enhance the data retention time for operation at near-threshold voltage (NTV). First, a 3-transistor (3T) gain-cell (GC) using a full transmission gate (TG) write port is presented. This full TG 3T GC bitcell allows fast write operations as well as memory operation at a single supply voltage, whereas conventional 2-transistor (2T) GC-eDRAMs require a write word-line (WWL) boost in addition to the main supply voltage. Furthermore, the full TG 3T GC bitcell enables strong initial data levels on the storage node (SN) for extended retention times. Next, the impact of body biasing on a 3T GC-eDRAM is analyzed. Silicon measurements of a test array implemented in 0.18 μm CMOS technology show that reverse body biasing (RBB) can significantly extend the retention time. Finally, as an assist technique to reduce accumulated pessimism from assuming worst-case process, voltage, temperature (PVT) conditions and write disturb activities, a replica technique for optimum refresh timing is presented, and its effectiveness is demonstrated through silicon measurements.
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Notes
- 1.
In an extremely unlikely case this calibration would be insufficient. This would happen if a continuous write “1” operation was applied to a column with a bitcell with worse retention time than the worst replica cell. However, this scenario would hardly ever occur in any real application. Otherwise, it is still possible to impose a write access policy to the array, which, for example, allows to write to the array only every second clock cycle. In addition, to avoid such a write access policy, it is possible to limit the WBL pulse time for the storage array, while using a pulse width equal to a full clock cycle for the replica columns.
- 2.
The victim address will always store 0xFFFFFFFF, and therefore is not considered for comparison with expected responses.
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Meinerzhagen, P., Teman, A., Giterman, R., Edri, N., Burg, A., Fish, A. (2018). Novel Bitcells and Assist Techniques for NTV GC-eDRAMs. In: Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip. Springer, Cham. https://doi.org/10.1007/978-3-319-60402-2_5
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