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Retention Time Modeling: The Key to Low-Power GC-eDRAMs

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Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

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Abstract

As seen in Chap. 2, gain-cell (GC) embedded DRAM (eDRAM), or GC-eDRAM in short, is an interesting alternative to static random-access memory (SRAM) and 1-transistor-1-capacitor (1T-1C) eDRAM for reasons, such as high storage density, low bitcell leakage, logic compatibility, and suitability for two-port memories. The major drawbacks of GC-eDRAMs are their limited data retention times (RTs) and the large spread of RT across an array (Chun et al., IEEE J Solid State Circuits 47(10):2517–2526, 2012; Meinerzhagen et al., IET J Eng 1, 2013), which limit energy-efficiency due to refresh cycles. While the array refresh rate can be determined by circuit simulations or post-silicon measurements, there is a lack of analytical and statistical GC-eDRAM RT models unveiling the circuit parameters, which lead to the large observed RT spreads. This chapter derives a comprehensive analytical model for the nominal value, as well as the statistical distribution of the per-cell retention time of 2-transistor (2T)-bitcell GC-eDRAMs, which is found to follow a log-normal distribution. The accuracy of the proposed retention time model is verified by extensive Monte Carlo (MC) and worst-case distance circuit simulations, as well as silicon measurements of an 0.18 µm test chip. Furthermore, a sensitivity analysis unveils the circuit parameters that have the highest impact on the RT spread. Interestingly, the variability of the threshold voltage of the write transistor (MW) has a much higher impact on the RT spread than the variability of any other circuit parameter, including the storage node (SN) capacitor. The insights gained from the retention time model help circuit designers achieve longer RTs and sharper RT distributions, which are key enablers for low-power GC-eDRAM designs. To summarize the learnings from this chapter, best-practice 2T GC design guidelines are presented.

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Notes

  1. 1.

    This holds true for the applicable range of V SN(t 0) < V SN < V EDRT.

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Authors and Affiliations

  1. Intel Labs, Circuit Research Lab, Intel Corporation, Hillsboro, Oregon, USA

    Pascal Meinerzhagen

  2. Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel

    Adam Teman, Robert Giterman, Noa Edri & Alexander Fish

  3. EPFL STI IEL TCL, Lausanne, Switzerland

    Andreas Burg

Authors
  1. Pascal Meinerzhagen
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  2. Adam Teman
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  3. Robert Giterman
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  4. Noa Edri
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  5. Andreas Burg
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  6. Alexander Fish
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Meinerzhagen, P., Teman, A., Giterman, R., Edri, N., Burg, A., Fish, A. (2018). Retention Time Modeling: The Key to Low-Power GC-eDRAMs. In: Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip. Springer, Cham. https://doi.org/10.1007/978-3-319-60402-2_3

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  • DOI: https://doi.org/10.1007/978-3-319-60402-2_3

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-60401-5

  • Online ISBN: 978-3-319-60402-2

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