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International Conference on Reversible Computation

RC 2017: Reversible Computation pp 77–89Cite as

Designing Parity Preserving Reversible Circuits

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Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 10301))

Abstract

With the emergence of reversible circuits as an energy-efficient alternative of classical circuits, ensuring fault tolerance in such circuits becomes a very important problem. Parity-preserving reversible logic design is one viable approach towards fault detection. Interestingly, most of the existing designs are ad hoc, based on some pre-defined parity preserving reversible gates as building blocks. In the current work, we propose a systematic approach towards parity preserving reversible circuit design. We prove a few theoretical results and present two algorithms, one from reversible specification to parity preserving reversible specification and another from irreversible specification to parity preserving reversible specification. We derive an upper-bound for the number of garbage bits for our algorithm and perform its complexity analysis. We also evaluate the effectiveness of our approach by extensive experimental results and compare with the state-of-the-art practices. To our knowledge, this is the first work towards systematic design of parity preserving reversible circuit and more research is needed in this area to make this approach more scalable.

The original version of this chapter was revised: Table 2 was corrected. An erratum to this chapter can be found at 10.1007/978-3-319-59936-6_20

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Author information

Authors and Affiliations

  1. Cryptology and Security Research Unit (CSRU), R.C. Bose Centre for Cryptology and Security, Indian Statistical Institute, Kolkata, 700 108, India

    Goutam Paul

  2. School of Computer Engineering, Nanyang Technological University (NTU), Singapore, Singapore

    Anupam Chattopadhyay

  3. Liv Artificial Intelligence Pvt. Ltd., Bengaluru, India

    Chander Chandak

Authors
  1. Goutam Paul
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  2. Anupam Chattopadhyay
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  3. Chander Chandak
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Corresponding author

Correspondence to Goutam Paul .

Editor information

Editors and Affiliations

  1. Imperial College London, London, United Kingdom

    Iain Phillips

  2. Indian Institute of Engineering Science and Technology, Shibpur, India

    Hafizur Rahaman

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Paul, G., Chattopadhyay, A., Chandak, C. (2017). Designing Parity Preserving Reversible Circuits. In: Phillips, I., Rahaman, H. (eds) Reversible Computation. RC 2017. Lecture Notes in Computer Science(), vol 10301. Springer, Cham. https://doi.org/10.1007/978-3-319-59936-6_6

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  • DOI: https://doi.org/10.1007/978-3-319-59936-6_6

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-59935-9

  • Online ISBN: 978-3-319-59936-6

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