Abstract
Logical reversibility is the basis for emerging technologies like quantum computing, may be used for certain aspects of low-power design, and has been proven beneficial for the design of encoding/decoding devices. Testing of circuits has been a major concern to verify the integrity of the implementation of the circuit. In this paper, we propose the main ideas of an ATPG method for detecting two missing gate faults. To that effect, we propose a systematic flow using Binary Decision Diagrams (BDDs). Initial experimental results demonstrate the efficacy of the proposed algorithms in terms of scalability and coverage of all testable faults.
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This work has partially been supported by the EU COST Action IC1405.
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Surhonne, A.P., Chattopadhyay, A., Wille, R. (2017). Automatic Test Pattern Generation for Multiple Missing Gate Faults in Reversible Circuits. In: Phillips, I., Rahaman, H. (eds) Reversible Computation. RC 2017. Lecture Notes in Computer Science(), vol 10301. Springer, Cham. https://doi.org/10.1007/978-3-319-59936-6_14
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DOI: https://doi.org/10.1007/978-3-319-59936-6_14
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