Abstract
The Chapter is devoted to hardware reduction targeting the normal LCS-based Moore FSMs. Firstly, the optimization methods are proposed for the base model of NFSM. They are based on the executing either optimal state assignment or transformation of state codes. Two different models are proposed for the case of code transformation. They depend on the numbers of microoperations of FSM and outputs of EMB in use. The models are discussed based on the principle of code sharing. In this case, the state code is represented as a concatenation of the code of normal LCS and the code of component inside this chain. The last part of the chapter is devoted to design methods targeting the hybrid FPGAs.
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Barkalov, A., Titarenko, L., Bieganowski, J. (2018). Hardware Reduction for Moore NFSMs. In: Logic Synthesis for Finite State Machines Based on Linear Chains of States. Studies in Systems, Decision and Control, vol 113. Springer, Cham. https://doi.org/10.1007/978-3-319-59837-6_7
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DOI: https://doi.org/10.1007/978-3-319-59837-6_7
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