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High-Speed Decoders for Polar Codes pp 55–71Cite as

Unrolled Hardware Architectures for Polar Decoders

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Abstract

In this chapter, we demonstrate that polar decoders can achieve extremely high throughput values and retain moderate complexity. We present a family of architectures for hardware polar decoders using a reduced-complexity successive-cancellation decoding algorithm that employ unrolling. The resulting fully-unrolled architectures are capable of achieving a coded throughput in excess 400 Gbps and 1 Tbps on an FPGA or an ASIC , respectively—two to three orders of magnitude greater than current state-of-the-art polar decoders—while maintaining a competitive energy efficiency of 6.9 pJ/bit on ASIC . Moreover, the proposed architectures are flexible in a way that makes it possible to explore the trade-off between area, throughput and energy efficiency . We present the associated results for a range of pipeline depths, and code lengths and rates. We also discuss how the throughput and complexity of decoders are effected when implemented for an I/O-bound system.

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Authors and Affiliations

  1. Institute of Electrical Engineering, École Polytechnique Fédérale de Lausanne, Lausanne, VD, Switzerland

    Pascal Giard

  2. Department of Electrical Engineering, École de Technologie Supérieure, Montréal, QC, Canada

    Claude Thibeault

  3. Department of Electrical and Computer Engineering, McGill University, Montréal, QC, Canada

    Warren J. Gross

Authors
  1. Pascal Giard
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  2. Claude Thibeault
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  3. Warren J. Gross
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Giard, P., Thibeault, C., Gross, W.J. (2017). Unrolled Hardware Architectures for Polar Decoders. In: High-Speed Decoders for Polar Codes. Springer, Cham. https://doi.org/10.1007/978-3-319-59782-9_4

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  • DOI: https://doi.org/10.1007/978-3-319-59782-9_4

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-59781-2

  • Online ISBN: 978-3-319-59782-9

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