Abstract
Low-power verification has become probably one of the most complex design verification problems to address under the design verification umbrella. Verification of low power is not simply restricted to checking for isolation cells, retention cells, and power domain ON/OFF conditions, but it also needs to check to see if the applied low-power techniques indeed improve the battery life without affecting performance!
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Bibliography
Report, S. T. (2008, September). Low power design, special technology report. SCDsource.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG
About this chapter
Cite this chapter
Mehta, A.B. (2018). Low-Power Verification. In: ASIC/SoC Functional Design Verification. Springer, Cham. https://doi.org/10.1007/978-3-319-59418-7_9
Download citation
DOI: https://doi.org/10.1007/978-3-319-59418-7_9
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-59417-0
Online ISBN: 978-3-319-59418-7
eBook Packages: EngineeringEngineering (R0)