Abstract
SystemVerilog Assertions (SVA) is one of the most important components of SystemVerilog when it comes to design verification. SVA is instrumental in finding corner cases, ease of debug, and coverage of design’s sequential logic. We will discuss high-level SVA methodology, SVA and functional coverage-driven methodology, and plenty of applications to solidify the concepts.
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Bibliography
Mehta, A. (2016). SystemVerilog assertions and functional coverage. A comprehensive guide to methodologies and applications. Los Gatos: Springer.
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Mehta, A.B. (2018). SystemVerilog Assertions (SVA). In: ASIC/SoC Functional Design Verification. Springer, Cham. https://doi.org/10.1007/978-3-319-59418-7_6
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DOI: https://doi.org/10.1007/978-3-319-59418-7_6
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Publisher Name: Springer, Cham
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Online ISBN: 978-3-319-59418-7
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